Hitachi SH7032 - Page 14

Section Page Description Edition
19.1.2 Register
Table 19.2 Standby
Control Register
(SBYCR)
460 Note added
Name Abbreviation R/W Initial Value Address* Access size
Standby control register SBYCR R/W H'1F H'5FFFFBC 8, 16, 32
Note: * Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
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20.1.2 DC
Characteristics
Table 20.2 DC
Characteristics
467 16.6 MHz deleted 6
Table 20. 2 DC
Characteristics
 Table of 16.6 MHz deleted 6
Table 20.3
Permitted Output
Current Values
471 16.6 MHz deleted 6
20.1.3 AC
Characteristics
(1) Clock Timing
Table 20.4 Clock
Timing
472 16.6 MHz deleted 6
(2) Control Signal
Timing
Table 20.5 Control
Signal Timing
474 16.6 MHz deleted 6
(3) Bus Timing
Table 20.6 Bus
Timing (1)
478,
479
Description amended
Read data access time 1
*
6
t
ACC1
t
cyc
– 30
*
4
— ns 20.8, 20.11, 20.12
Read data access time 2
*
6
t
ACC2
t
cyc
× (n+2) –
30
*
3
— ns 20.9, 20.10,
20.13–20.15
Read data access time from
CAS 2
*
6
t
CAC2
t
cyc
× (n+1) –
25
*
3
—ns
Read data access time from
RAS 1
*
6
t
RAC1
t
cyc
× 1.5 – 20 — ns 20.11, 20.12
Read data access time from
RAS 2
*
6
t
RAC2
t
cyc
× (n+2.5)
– 20
*
3
—ns
20.13–20.15
20.13–20.15

Data setup time for CAS t
DS
0
*
5
— ns 20.11, 20.13
CAS setup time for RAS t
CSR
10 — ns 20.16–20.18
Row address hold time t
RAH
10 — ns 20.11, 20.13
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Table 20.7 Bus
Timing (2)

Table deleted
6
Table 20.7 Bus
Timing (2)
494 Description amended
Read data access time 1
*
4
t
ACC1
t
cyc
– 44 — ns 20.21, 20.24, 20.25
Read data access time 2
*
4
t
ACC2
t
cyc
× (n+2) – 44
*
2
— ns 20.22, 20.23,
20.26–20.28
6