Hitachi SH7032 - Page 13

Section Page Description Edition
12.2.2 Timer
Control/Status
Register (TCSR)
338 Note added
Note: * Only 0 can be written, to clear the flag.
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13.2.6 Serial Control
Register
359 Initial value added
Internal clock, SCK pin used for input pin (input signal
is ignored) or output pin (output level is undefined)
*
2
(Initial value)
Internal clock, SCK pin used for serial clock output
*
2
(Initial value)
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13.2.8 Bit Rate
Register (BRR)
Table 13.3 Bit Rates
and BRR Settings in
Asynchronous Mode
367 Note added
Note: Settings with an error of 1% or less are recommended.
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Table 13.4 Bit
Rates and BRR
Settings in
Synchronous Mode
368 Note deleted 6
15.2 Register
Configuration
Table 15.2 Pin
Function Controller
Registers
427 Note added
Name Abbreviation R/W Initial Value Address* Access Size
Port A I/O register PAIOR R/W H'0000 H'5FFFFC4 8, 16, 32
Port A control register 1 PACR1 R/W H'3302 H'5FFFFC8 8, 16, 32
Port A control register 2 PACR2 R/W H'FF95 H'5FFFFCA 8, 16, 32
Port B I/O register PBIOR R/W H'0000 H'5FFFFC6 8, 16, 32
Port B control register 1 PBCR1 R/W H'0000 H'5FFFFCC 8, 16, 32
Port B control register 2 PBCR2 R/W H'0000 H'5FFFFCE 8, 16, 32
Column address strobe
pin control register
CASCR R/W H'5FFF H'5FFFFEE 8, 16, 32
Note: * Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
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16.2.1 Register
Configuration
Table 16.1 Port A
Register
442 Note added
Name Abbreviation R/W Initial Value Address* Access Size
Port A data register PADR R/W H'0000 H'5FFFFC0 8, 16, 32
Note: * Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
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16.3.1 Register
Configuration
Table 16.3 Port B
Register
443 Note added
Name Abbreviation R/W Initial Value Address* Access Size
Port B data register PBDR R/W H'0000 H'5FFFFC2 8, 16, 32
Note: * Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
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16.4.1 Register
Configuration
Table 16.5 Port C
Register
445 Note added
Name Abbreviation R/W Initial Value Address* Access Size
—
Note: * Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
Port C data register PCDR R/W H'5FFFFD0 8, 16, 32
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