209
CK
DREQ
DACK
Bus cycle
TcTrTp Tc
CPU DMAC(R) DMAC (R)
TcTrTp Tc
CPUCPU
DMAC
(W)
CPU
DMAC
(W)
CPU
DMAC (R): DMAC read cycle
DMAC (W): DMAC write cycle
Note: When DREQ is negated at the fourth state of the DMAC cycle, the next DMA transfer will
be executed because the sampling is performed at the second state of the DMAC cycle.
Figure 9.20 DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ Level
Detection and DACK Active-Low) (Dual Address Mode, Bus Cycle = DRAM Bus Cycle
(Long Pitch Normal Mode))
CK
DREQ
DACK
Bus cycle
T3T2T1 T4
CPUCPUCPU DMACCPU CPU
T3T2T1 T4
DMAC
Note: When DREQ is negated at the fourth state of the DMAC cycle, the next DMA transfer will
be executed because the sampling is performed at the second state of the DMAC cycle.
Figure 9.21 DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ Level
Detection and DACK Active-Low) (Single Address Mode, Bus Cycle = Address/Data
Multiplex I/O Bus Cycle)
To Next Page
Loading...
