208
DMAC (R): DMAC read cycle
DMAC (W): DMAC write cycle
CK
DREQ
DACK
Bus cycle
T2TwT1
CPUCPU DMAC (R)CPU CPU
T2TwT1
CPUDMAC (W)
Figure 9.18 DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ Level
Detection and DACK Active-Low) (Dual Address Mode, Bus Cycle = 2 States + 1 Wait State)
CK
DREQ
DACK
Bus cycle
TcTrTp Tc
CPUCPUCPU DMACCPU CPU
TcTrTp Tc
DMAC
Note: When DREQ is negated at the fourth state of the DMAC cycle, the next DMA transfer will
be executed because the sampling is performed at the second state of the DMAC cycle.
Figure 9.19 DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ Level
Detection and DACK Active-Low) (Single Address Mode, Bus Cycle = DRAM Bus Cycle
(Long Pitch Normal Mode))
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