Hitachi SH7032 - Page 340

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Table 10.21 ITU Operating Modes (Channel 3) (cont)
Register Setting
TSNC TMDR TFCR TOCR TIOR3 TCR3
Operating
Mode Sync MDF FDIR PWM
Comp
PWM
Reset
Sync
PWM Buffer
Output
Level
Select IOA IOB
Clear
Select
Clock
Select
Comple-
mentary
PWM mode
√
*
2
— — — CMD1
= 1
CMD0
= 0
CMD1
= 1
CMD0
= 0
√√— — CCLR1
= 0
CCLR0
= 0
√
*
4
Reset
synchron-
ized PWM
mode
√ — — — CMD1
= 1
CMD0
= 1
CMD1
= 1
CMD0
= 1
√√— — CCLR1
= 0
CCLR0
= 1
√
Buffer
(BRA)
√ ——√√√BFA3 =
1,
others:
don’t
care
— √√ √√
Buffer
(BRB)
√ ——√√√BFB3 =
1,
others:
don’t
care
— √√ √√
√: Settable, —: Setting does not affect current mode
Notes: *1 In PWM mode, the input capture function cannot be used. When compare match A and
compare match B occur simultaneously, the compare match signal is inhibited.
*2 When set for complementary PWM mode, do not simultaneously set channel 3 and
channel 4 to function synchronously.
*3 Counter clearing by input capture A cannot be used when reset-synchronized PWM
mode is set.
*4 Clock selection when complementary PWM mode is set should be the same for
channels 3 and 4.