Hitachi SH7032 - Page 341

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Table 10.22 ITU Operating Modes (Channel 4)
Register Setting
TSNC TMDR TFCR TOCR TIOR4 TCR4
Operating
Mode Sync MDF FDIR PWM
Comp
PWM
Reset
Sync
PWM Buffer
Output
Level
Select IOA IOB
Clear
Select
Clock
Select
Synch-
ronized
preset
SYNC4
= 1
—— √√
*
2
√√ — √√ √√
PWM √ — — PWM4
= 1
CMD1
= 0
CMD1
= 0
√ —— √
*
1
√√
Output
compare A
function
√ — — PWM4
= 0
CMD1
= 0
CMD1
= 0
√ — IOA2 = 0,
others:
don’t care
√√√
Output
compare B
function
√ —— √ CMD1
= 0
CMD1
= 0
√ — √ IOB2 = 0,
others:
don’t care
√√
Input
capture A
function
√ — — PWM4
= 0
CMD1
= 0
CMD1
= 0
√ — IOA2 = 1,
others:
don’t care
√√√
Input
capture B
function
√ — — PWM4
= 0
CMD1
= 0
CMD1
= 0
√ — √ IOB2 = 1,
others:
don’t care
√√
Counter Clear Function
Clear at
compare
match/
input
capture A
√ —— √ CMD1
= 1,
CMD0
= 0
inhib-
ited
√
*
3
√ — √√ CCLR1
= 0
CCLR0
= 1
√
Clear at
compare
match/
input
capture B
√ —— √ CMD1
= 1,
CMD0
= 0
inhib-
ited
√
*
3
√ — √√ CCLR1
= 1
CCLR0
= 0
√
Synch-
ronized
clear
SYNC4
= 1
—— √ CMD1
= 1,
CMD1
= 0
inhib-
ited
√
*
3
√ — √√ CCLR1
= 1
CCLR0
= 1
√