Hitachi SH7032 - Page 465

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• Bits 7 and 6 (PA11 Mode (PA11MD1 and PA11MD0)): PA11MD1 and PA11MD0 select the
function of the PA11/DPH/TIOCB1 pin.
Bit 7:
PA11MD1
Bit 6:
PA11MD0 Function
0 0 Input/output (PA11) (Initial value)
1 Upper data bus parity input/output (DPH)
1 0 ITU input capture/output compare (TIOCB1)
1 Reserved
• Bits 5 and 4 (PA10 Mode (PA10MD1 and PA10MD0)): PA10MD1 and MA10MD0 select the
function of the PA10/DPL/TIOCA1 pin.
Bit 5:
PA10MD1
Bit 4:
PA10MD0 Function
0 0 Input/output (PA10) (Initial value)
1 Lower data bus parity input/output (DPL)
1 0 ITU input capture/output compare (TIOCA1)
1 Reserved
• Bits 3 and 2 (PA9 Mode (PA9MD1 and PA9MD0)): PA9MD1 and PA9MD0 select the
function of the PA9/AH/IRQOUT/ADTRG pin.
Bit 3:
PA9MD1
Bit 2:
PA9MD0 Function
0 0 Input/output (PA9) (Initial value)
1 Address hold output (AH)
1 0 A/D conversion trigger input (ADTRG)
1 Interrupt request output (IRQOUT)
• Bit 1 (Reserved): This bit is always read as 1. The write value should always be 1.
• Bit 0 (PA8 Mode (PA8MD)): PA8MD selects the function of the PA8/BREQ pin.
Bit 0: PA8MD Function
0 Input/output (PA8) (Initial value)
1 Bus request input (BREQ)