Hitachi SH7032 - Page 518

483
CK
A21–A0
RAS
CAS
WRH, WRL,
WR(Read)
DACK0
DACK1
(Read)
AD15–AD0
DPH, DPL
(Read)
WRH, WRL,
WR(Write)
AD15–AD0
(Write)
DPH, DPL
(Write)
DACK0
DACK1
(Write)
T
p
T
r
T
c
t
AD
t
AD
t
RASD1
t
RASD2
t
CASD1
t
DACD1
t
CAC1
*
1
t
RDS
t
RDH
*
4
t
WSD3
t
WDD2
t
WDH
t
WPDD2
t
WPDH
t
DACD4
t
DACD5
t
ACC1
*
2
t
RAH
t
DACD2
t
WSD4
t
WCH
t
ASC
t
DS
Row Column
t
WCS
t
RAC1
*
3
RD(Write)
RD(Read)
t
RSD
t
RDD
Notes: *1 For t
CAC1
, use t
cyc
× 0.65 – 19 (for 35% duty) or t
cyc
× 0.5 – 19 (for 50% duty) instead of
t
cyc
– t
AD
– t
ASC
– t
RDS
.
*2 For t
ACC1
, use t
cyc
– 30 instead of t
cyc
– t
AD
– t
RDS
.
*3 For t
RAC1
, use t
cyc
× 1.5 – 20 instead of t
cyc
× 1.5 – t
RASD1
– t
RDS
.
*4t
RDH
is measured from A21–A0, RAS, or CAS, whichever is negated first.
Figure 20.11 DRAM Bus Cycle (Short-Pitch, Normal Mode)