Hitachi SH7032 - Page 517

482
DACK0
DACK1
(Read)
RD
(Read)
CSn
AD15–AD0
DPH, DPL
(Read)
A21–A0
HBS, LBS
DACK0
DACK1
(Write)
CK
WAIT
AD15–AD0
DPH, DPL
(Write)
WRH, WRL,
WR (Write)
T
1
T
W
T
2
t
WTS
t
WTH
t
WTS
t
WTH
t
RDAC2
*
1
t
ACC2
*
2
Notes: *1 For t
RDAC2
, use t
cyc
× (n+1.65) – 20 (for 35% duty) or t
cyc
× (n+1.5) – 20 (for 50% duty)
instead of t
cyc
× (n+2) – t
RDD
– t
RDS
.
*2 For t
ACC2
, use t
cyc
× (n+2) – 30 instead of t
cyc
× (n+2) – t
AD
(or t
CSD1
) – t
RDS
.
Figure 20.10 Basic Bus Cycle: Two States + Wait State