Hitachi SH7032 - Page 528

493
Table 20.7 Bus Timing (2)
Conditions: V
CC
= 3.0 to 5.5 V, AV
CC
= 3.0 to 5.5 V, AV
CC
= V
CC
±10%, AV
ref
= 3.0 V to
AV
CC
, V
SS
= AV
SS
= 0 V, φ = 12.5 MHz, Ta = –20 to +75°C
*
Note: * Regular-specification products; for wide-temperature-range products, Ta = –40 to +85°C
Item Symbol Min Max Unit Figures
Address delay time t
AD
— 40 ns 20.21, 20.22, 20.24–
20.27, 20.32, 20.33
CS delay time 1 t
CSD1
— 40 ns 20.21, 20.22, 20.33
CS delay time 2 t
CSD2
—40ns
CS delay time 3 t
CSD3
— 40 ns 20.32
CS delay time 4 t
CSD4
—40ns
Access time 1
*
4
35% duty
*
1
t
RDAC1
t
cyc
× 0.65 – 35 — ns 20.21,
from read strobe
50% duty t
cyc
× 0.5 – 35 — ns
Access time 2
*
4
35% duty
*
1
t
RDAC2
t
cyc
× (n+1.65) – 35
*
2
— ns 20.22, 20.23
from read strobe
50% duty t
cyc
× (n+1.5) – 35
*
2
—ns
Access time 3
*
4
35% duty
*
1
t
RDAC3
t
cyc
× (n+0.65) – 35
*
2
— ns 20.32
from read strobe
50% duty t
cyc
× (n+0.5) – 35
*
2
—ns
Read strobe delay time t
RSD
— 40 ns 20.21, 20.22,
20.24–20.28, 20.32
Read data setup time t
RDS
25 — ns 20.21, 20.22,
Read data hold time t
RDH
0 — ns 20.24-20.27, 20.32
Write strobe delay time 1 t
WSD1
— 40 ns 20.22, 20.26, 20.27,
20.32, 20.33
Write strobe delay time 2 t
WSD2
— 30 ns 20.22, 20.26, 20.27,
20.32
Write strobe delay time 3 t
WSD3
— 40 ns 20.24, 20.25
Write strobe delay time 4 t
WSD4
— 40 ns 20.24, 20.25, 20.33
Write data delay time 1 t
WDD1
— 70 ns 20.22, 20.26, 20.27,
20.32
Write data delay time 2 t
WDD2
— 40 ns 20.24, 20.26
Write data hold time t
WDH
–10 — ns 20.22, 20.24–20.27,
20.32
Parity output delay time 1 t
WPDD1
— 80 ns 20.22, 20.24, 20.27
Parity output delay time 2 t
WPDD2
— 40 ns 20.24, 20.25
Parity output hold time t
WPDH
–10 — ns 20.22, 20.23–20.27