Hitachi SH7032 - Page 529

494
Table 20.7 Bus Timing (2) (cont)
Conditions: V
CC
= 3.0 to 5.5 V, AV
CC
= 3.0 to 5.5 V, AV
CC
= V
CC
±10%, AV
ref
= 3.0 V to
AV
CC
, V
SS
= AV
SS
= 0 V, φ = 12.5 MHz, Ta = –20 to +75°C
*
Note: * Regular-specification products; for wide-temperature-range products, Ta = –40 to +85°C
Item Symbol Min Max Unit Figures
Wait setup time t
WTS
40 — ns 20.23, 20.28, 20.32
Wait hold time t
WTH
10 — ns
Read data access time 1
*
4
t
ACC1
t
cyc
– 44 — ns 20.21, 20.24, 20.25
Read data access time 2
*
4
t
ACC2
t
cyc
× (n+2) – 44
*
2
— ns 20.22, 20.23,
20.26–20.28
RAS delay time 1 t
RASD1
— 40 ns 20.24–20.27, 20.29–
RAS delay time 2 t
RASD2
—40ns
20.31
CAS delay time 1 t
CASD1
— 40 ns 20.24
CAS delay time 2
*
5
t
CASD2
— 40 ns 20.26, 20.27, 20.29–
CAS delay time 3
*
5
t
CASD3
—40ns
20.31
Column address setup time t
ASC
0 — ns 20.24, 20.25
Read data 35% duty
*
1
t
CAC1
t
cyc
× 0.65 – 35 — ns
access time from
CAS 1
*
4
50% duty t
cyc
× 0.5 – 35 — ns
Read data access time from
CAS 2
*
4
t
CAC2
t
cyc
× (n+1) – 35
*
2
— ns 20.26–20.28
Read data access time from
RAS 1
*
4
t
RAC1
t
cyc
× 1.5 – 35 — ns 20.24, 20.25
Read data access time from
RAS 2
*
4
t
RAC2
t
cyc
× (n+2.5) – 35
*
2
— ns 20.26–20.28
High-speed page mode CAS
precharge time
t
CP
t
cyc
× 0.25 — ns 20.25
AH delay time 1 t
AHD1
— 40 ns 20.32
AH delay time 2 t
AHD2
—40ns
Multiplexed address delay
time
t
MAD
—40ns
Multiplexed address hold
time
t
MAH
–10 — ns