Hitachi SH7032 - Page 530

495
Table 20.7 Bus Timing (2) (cont)
Conditions: V
CC
= 3.0 to 5.5 V, AV
CC
= 3.0 to 5.5 V, V
CC
= AV
CC
±10%, AV
ref
= 3.0 V to
AV
CC
, V
SS
= AV
SS
= 0 V, φ = 12.5 MHz, Ta = –20 to +75°C
*
Note:
*
Regular-specification products; for wide-temperature-range products, Ta = –40 to +85°C
Item Symbol Min Max Unit Figures
DACK0, DACK1 delay time 1 t
DACD1
— 40 ns 20.21, 20.22, 20.24–
DACK0, DACK1 delay time 2 t
DACD2
—40 ns
20.27, 20.32, 20.33
DACK0, DACK1 delay time 3
*
5
t
DACD3
— 40 ns 20.22, 20.26, 20.27,
20.32
DACK0, DACK1 delay time 4 t
DACD4
— 40 ns 20.24, 20.25
DACK0, DACK1 delay time 5 t
DACD5
—40 ns
Read delay time 35% duty
*
1
t
RDD
—t
cyc
× 0.35 + 35 ns 20.21, 20.22, 20.24-
50% duty — t
cyc
× 0.5 + 35 ns
20.28, 20.32
Data setup time for CAS t
DS
0
*
3
— ns 20.24, 20.26
CAS setup time for RAS t
CSR
10 — ns 20.29–20.31
Row address hold time t
RAH
10 — ns 20.24, 20.26
Write command hold time t
WCH
15 — ns
Write command 35% duty
*
1
t
WCS
0 — ns 20.24
setup time
50% duty t
WCS
0— ns
Access time from CAS
precharge
*
4
t
ACP
tcyc
–20
— ns 20.25
Notes: *1 When frequency is 10 MHz or more.
*2 n is the number of wait cycles.
*3 –5 ns for parity output of DRAM long-pitch access
*4 It is not necessary to meet the t
RDS
specification as long as the access time
specification is met.
*5 In the relationship of t
CASD2
and t
CASD3
with respect to t
DACD3
, a Min-Max combination
does not occur because of the logic structure.