Hitachi SH7032 - Page 535

500
CK
A21–A0
RAS
CAS
WRH, WRL
,
WR
(Read)
DACK0
DACK1
(Read)
AD15–AD0
DPH, DPL
(Read)
t
AD
T
p
T
r
T
c
T
c
T
c
t
AD
t
RASD1
t
RASD2
t
CP
t
ASC
t
RDH
*
5
t
RAC1
*3
t
DACD1
t
DACD2
Row address Column address Column address Column address
t
CAC1
*1
T
c
t
ACC1
*2
t
RDS
RD(Read)
t
RDD
t
ACP
t
RSD
t
RDH
*4
Column address
Notes: *1 For t
CAC1
, use t
cyc
× 0.65 – 35 (for 35% duty) or t
cyc
× 0.5 – 35 (for 50% duty) instead of
t
cyc
– t
AD
– t
ASC
– t
RDS
.
It is not necessary to meet the t
RDS
specification as long as the t
CAC1
specification is met.
*2 For t
ACC1
, use t
cyc
– 44 instead of t
cyc
– t
AD
– t
RDS
.
It is not necessary to meet the t
RDS
specification as long as the t
ACC1
specification is met.
*3 For t
RAC1
, use t
cyc
× 1.5 – 35 instead of t
cyc
× 1.5 – t
RASD1
– t
RDS
.
It is not necessary to meet the t
RDS
specification as long as the t
RAC1
specification is met.
*4t
RDH
is measured from A21—A0 or CAS, whichever is negated first.
*5t
RDH
is measured from A21—A0, RAS, or CAS, whichever is negated first.
Figure 20.25 (a) DRAM Bus Cycle (Short-Pitch, High-Speed Page Mode: Read)