502
CK
A21–A0
RAS
CAS
WRH, WRL,
WR(Read)
DACK0
DACK1
(Read)
AD15–AD0
DPH, DPL
(Read)
WRH, WRL,
WR(Write)
AD15–AD0
(Write)
t
AD
T
p
T
r
Tc
1
Tc
2
t
AD
t
RASD1
t
RASD2
DACK0
DACK1
(Write)
DPH, DPL
(Write)
Column
t
CASD3
t
RDH
*4
t
RDS
t
DACD1
t
DACD2
t
WSD1
t
WSD2
t
WDD1
t
WDH
t
WPDH
t
WPDD1
t
DACD3
t
DACD3
t
RAH
t
ACC2
*2
t
RAC2
*3
t
CASD2
t
DS
t
CAC2
*1
t
WCH
RD(Write)
RD(Read)
t
RDD
t
RSD
Row
Notes: *1 For t
CAC2
, use t
cyc
× (n + 1) – 35 instead of t
cyc
× (n + 1) – t
CASD2
– t
RDS
.
*2 For t
ACC2
, use t
cyc
× (n + 2) – 44 instead of t
cyc
× (n + 2) – t
AD
– t
RDS
.
*3 For t
RAC2
, use t
cyc
× (n + 2.5) – 35 instead of t
cyc
× (n + 2.5) – t
RASD1
– t
RDS
.
*4t
RDH
is measured from A21–A0, CAS, or RAS, whichever is negated first.
Figure 20.26 DRAM Bus Cycle: (Long-Pitch, Normal Mode)
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