Hitachi SH7032 - Page 73

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Table 2.14 Logic Operation Instructions
Instruction Instruction Code Operation
Execution
Cycles T Bit
AND Rm,Rn 0010nnnnmmmm1001 Rn & Rm → Rn 1 —
AND #imm,R0 11001001iiiiiiii R0 & imm → R0 1 —
AND.B #imm,@(R0,GBR) 11001101iiiiiiii (R0 + GBR) & imm
→ (R0 + GBR)
3—
NOT Rm,Rn 0110nnnnmmmm0111 ~Rm → Rn 1 —
OR Rm,Rn 0010nnnnmmmm1011 Rn | Rm → Rn 1 —
OR #imm,R0 11001011iiiiiiii R0 | imm → R0 1 —
OR.B #imm,@(R0,GBR) 11001111iiiiiiii (R0 + GBR) | imm →
(R0 + GBR)
3—
TAS.B @Rn 0100nnnn00011011 If (Rn) is 0, 1 → T; 1
→ MSB of (Rn)
4 Test
result
TST Rm,Rn 0010nnnnmmmm1000 Rn & Rm; if the
result is 0, 1 → T
1 Test
result
TST #imm,R0 11001000iiiiiiii R0 & imm; if the
result is 0, 1 → T
1 Test
result
TST.B #imm,@(R0,GBR) 11001100iiiiiiii (R0 + GBR) & imm;
if the result is 0, 1 →
T
3 Test
result
XOR Rm,Rn 0010nnnnmmmm1010 Rn ^ Rm → Rn 1 —
XOR #imm,R0 11001010iiiiiiii R0 ^ imm → R0 1 —
XOR.B #imm,@(R0,GBR) 11001110iiiiiiii (R0 + GBR) ^ imm
→ (R0 + GBR)
3—