39
Table 2.15 Shift Instructions
Instruction Instruction Code Operation Execution Cycles T Bit
ROTL Rn 0100nnnn00000100 T ← Rn ← MSB 1 MSB
ROTR Rn 0100nnnn00000101 LSB → Rn → T 1 LSB
ROTCL Rn 0100nnnn00100100 T ← Rn ← T 1 MSB
ROTCR Rn 0100nnnn00100101 T → Rn → T 1 LSB
SHAL Rn 0100nnnn00100000 T ← Rn ← 0 1 MSB
SHAR Rn 0100nnnn00100001 MSB → Rn → T 1 LSB
SHLL Rn 0100nnnn00000000 T ← Rn ← 0 1 MSB
SHLR Rn 0100nnnn00000001 0 → Rn → T 1 LSB
SHLL2 Rn 0100nnnn00001000 Rn<<2 → Rn 1 —
SHLR2 Rn 0100nnnn00001001 Rn>>2 → Rn 1 —
SHLL8 Rn 0100nnnn00011000 Rn<<8 → Rn 1 —
SHLR8 Rn 0100nnnn00011001 Rn>>8 → Rn 1 —
SHLL16 Rn 0100nnnn00101000 Rn<<16 → Rn 1 —
SHLR16 Rn 0100nnnn00101001 Rn>>16 → Rn 1 —
Table 2.16 Branch Instructions
Instruction Instruction Code Operation
Execution
Cycles T Bit
BF label 10001011dddddddd If T = 0, disp × 2 + PC → PC; if T = 1,
nop
3/1
*
—
BT label 10001001dddddddd If T = 1, disp × 2 + PC → PC; if T = 0,
nop
3/1
*
—
BRA label 1010dddddddddddd Delayed branch, disp × 2 + PC → PC 2 —
BSR label 1011dddddddddddd Delayed branch, PC → PR, disp × 2 +
PC → PC
2—
JMP @Rm 0100mmmm00101011 Delayed branch, Rm → PC 2 —
JSR @Rm 0100mmmm00001011 Delayed branch, PC → PR, Rm → PC 2 —
RTS 0000000000001011 Delayed branch, PR → PC 2 —
Note: *The execution state is three cycles when program branches, and one cycle when program
does not branch.
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