HP 8753E - Page 375

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DSP WdRd. Verifies the ability of the main processor and the
DSP (digital signal processor), both on the A9 CPU assembly, to
communicate with each other through DRAM. This also verifies that
programs can be loaded to the DSP, and that most of the main RAM
access circuits operate correctly.
DSP RAM. Verifies the A9 CPU RAM associated with the digital signal
processor by using a write/read pattern.
DSP ALU. Verifies the A9 CPU high-speed math processing portions of
the digital signal processor.
DSP Intrpt. Tests the ability of the A9 CPU digitai signal processor to
respond to interrupts from the A10 digital IF ADC.
DIF Control. Tests the ability of the A9 CPU main processor to
write/read to the control latches on the A10 digitaI IF
DIF Canter. Tests the ability of the A9 CPU main processor to
write/read to the triple divider on the A10 CPU. It tests the A9
CPU data buffers and A10 digital IF, the 4 MHz clock from the Al2
reference.
DSP Control. Tests the ability of the A9 CPU digital signal processor to
write to the control latches on the A10 digital IF. Feedback is verified
by the main processor. It primarily tests the A10 digital IF, but failures
may be caused by the A9 CPU.
Fr F&n Wr/Rd. Tests the ability of the A9 CPU main processor to
write/read to the front panel processor. It tests the A2 front panel
interface and processor,and A9 CPU data buffering and address
decoding. (See also tests 23 and 24.) This runs only when selected.
Rear mel. Tests the ability of the A9 CPU main processor to
write/read to the rear panel control elements. It tests the Al6 rear
panel, and A9 CPU data buffering and address decoding. (It does not
test the HP-IB interface; for that, see the HP-IB Programming Guide.)
This runs only when selected or with ALL INTERNAL.
Post Reg. Polls the status register of the A8 post-regulator, and
flags these conditions: heat sink too hot, inadequate air flow, or
post-regulated supply shutdown.
Service Key Menus and Error Messages
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