HP 8753E - Source Low Band Operation

Source Low Band Operation
The low band frequency range is 300 kHz to 16 MHz. These frequencies are
generated by locking the A3 source to a reference signal. The reference signal
is synthesized by mixing down the fundamental output of the fractional-N VCO
with a 40 MHz crystal reference signal. Low band operation differs from high
band in these respects: The reference frequency for the All phase lock is not
a 6xed 1 MHz signal, but varies with the frequency of the fractional-N VCO
signal. The sampler diodes are biased on to pass the signal through to the mixer.
The 1st IF signal from the A4 sampler is not fixed but is identical to the source
output signal and sweeps with it. The following steps outline the low band
sweep sequence, illustrated in Figure 12-4.
1. A signal (FN LO) is generated by the fractional-N VCO. The VCO in the
Al4 Fractional-N assembly generates a CW or swept signal that is 40 MHz
greater than the start frequency. The signal is divided down to 100 kHz and
phase locked in the Al3 assembly, as in high band operation.
2. The fractional-N VCO signal is mixed with 40 MHZ to produce a
reference signal. The signal (F’N LO) from the Fractional-N VCO goes to the
Al2 reference assembly, where it is mixed with the 40 MHz VCXO (voltage
controlled crystal oscillator). The resulting signal is the reference to the
phase comparator in the All assembly.
3. The A3 source is pretuned. The source output is fed to the A4 sampler.
The pretuned DAC in the All phase lock assembly sets the A3 source to a
frequency 1 to 6 MHz above the start frequency. This signal (source output)
goes to the A4 R input sampler/mixer assembly.
4. The signal from the source is fed back (1st IF’) to the phase comparator.
The source output signal passes directly through the sampler in the A4
assembly, because the sampler is biased on. The signal (1st IF+) is fed back
unaltered to the phase comparator in the All phase lock assembly. The other
input to the phase comparator is the heterodyned reference signal from the
Al2 assembly. Any frequency difference between these two signals produces
a proportional error voltage.
5. A tuning signal (YO DRIVE) tunes the source and phase lock is achieved.
The error voltage is used to drive the A3 source YIG oscillator to bring the
YIG closer to the reference frequency. The loop process continues until the
source frequency and the reference frequency are the same, and phase lock
is achieved.
12-16 Theory of Operation