HP 8753E - Page 376

15
Frac N Cont. Tests the ability of the A9 CPU main processor to
write/read to the control element on the Al4 fractional-N (digital)
assembly. The control element must be functioning, and the
fractional-N VCO must be oscillating (although not necessarily
phase-locked) to pass.
16 Sweep Trig. Tests the sweep trigger (L SWP) Iine from the Al4
fractional-N to the A10 digital IF. The receiver with the sweep
synchronizes L SWP.
17
ADC Lin. It tests the linearity of the A10 digital IF ADC using the
built-in ramp generator. The test generates a histogram of the ADC
linearity, where each data point represents the relative “width” of a
particular ADC code.
Ideally, ah codes have the same width; different
widths correspond to non-Iinearities
18 ADC Ofs. This runs only when selected. It tests the ability of the
offset DAC, on the A10 digit& IF’, to apply a bias offset to the IF signals
before the ADC input. This runs only when selected.
19
ABUS ‘Wt. Tests analog bus accuracy, by measuring several analog bus
reference voltages (aII nodes from the A10 digitai IF). This runs only
when selected.
20 F’N Count. Uses the internal counter to count the Al4 fractional-N
VCO frequency (120 to 240 MHz) and the divided fractional-N
frequency (100 kHz). It requires the 100 kHz signal from Al2 and the
counter gate signal from A10 to pass
1 O-1 0 Service Key Menus and Error Messages