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The 604e and 750 have separate memory-management
units (MMUs) for instructions and data. The MMUs support
as many as 4 petabytes of virtual memory and 4 Gbytes of
physical memory. Access privileges and memory protection
are controlled on 128-kbyte to 256-Mbyte blocks and 4-kbyte
pages. Translation-look-aside buffers (TLBs) with 128 entries
efficiently translate addresses by storing the most recently
used page translations.
The 604e and 750 support 64-bit data and 32-bit address
buses. The interface protocol allows multiple masters to
access system resources through a central arbiter. The Power-
PC 604e works in multiprocessor systems and snooping tasks
and requires no additional bus cycles. The 604e’s on-chip
snooping logic maintains cache coherency in multiprocessor
systems. The 750 supports snooping but is optimized for
uniprocessor systems. It supports no data sharing among
caches in different processors. The buses on the 604e and 750
are compatible electrically and in the protocol they use. A
common chip set supports both processors.
The 603e comprises five parallel execution units: integer
execution, floating point, branch, system, and load/store.
With a four-stage pipeline—fetch, dispatch, execute, and
complete—the 603 can achieve three instructions per clock
cycle. During the fetch stage, the 603 uses a six-instruction
prefetch queue to hold pending instructions. Unlike other
PowerPC derivatives, the 603 supports only static branch pre-
diction. However, the architecture supports out-of-order exe-
cution and in-order retirement, similar to other PowerPC
devices.
The embedded PowerPC processors include IBM’s 400
series and Motorola’s MPC500 and MCP800 families and
devices. Compared with other PowerPC devices, these
devices have similar—but fewer—execution units. IBM’s
403Gx embedded controllers have a five-stage pipeline and
can dispatch as many as two instructions per cycle. These
devices implement static branch prediction and branch fold-
ing and have a four-instruction prefetch queue. Integrated
caches of varying sizes are two-way set-associative and are
implemented as fetch-through instruction caches and write-
back data caches. (The 403GCX data cache does not provide
write-through operation.) The 403Gx processors do not pro-
vide hardware support for maintaining cache coherency dur-
ing DMA and external bus-master operations or in a multi-
processor configuration.
The PowerPC 403GC and 403GCX include an MMU fea-
turing a fully associative TLB. Each entry provides translation
for a memory page, which can be one of several sizes for effi-
cient system-memory use. Memory components attach
directly to the 403 devices with a programmable-memory
interface on the processor’s bus-interface unit. The DRAM
controller includes the address multiplexer, eliminating the
need for an external address multiplexer. The DRAM con-
CIRCL
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troller supports external bus masters. You can use software
programming to tune the timing for the interface control sig-
nals.
The PowerPC 401GF implements a three-stage pipeline
and supports hardware multiply and divide and unaligned
loads and stores. The CPU uses operand forwarding and sta-
tic branch prediction to increase performance. The 401GF’s
cache controllers implement critical data forwarding, fill-
first handling of cache misses, and nonblocking flush oper-
ations.
Motorola’s MPC500 and MPC800 families, although tar-
geting different applications, have the same basic CPU archi-
tecture. (However, the new MPC8260 PowerQUICC II is an
upgrade of the MPC860 and contains a PowerPC EC603e
core.) Both families integrate a fixed-point unit (FXU), an
LSU, two register files, and a sequencer unit; the MPC500
family also adds an FPU. The FPU includes single- and dou-
ble-precision multiply-add instructions. The sequencer unit
contains a branch processor featuring static branch predic-
tion and branch-folding capability during execution (zero-
cycle branch execution time) and runtime reordering of loads
and stores.
The MPC500 and MPC800 devices use an InterModule
Bus, developed for Motorola’s 683xx devices, as a backplane
to connect all system modules. Both families include a sys-
tem-integration unit (SIU) that enables simple integration
with external memories, other CPUs, and peripherals. The
SIU for the MPC505 and MPC509 differs from the one in the
800 family devices and in the MPC555. The 505 and 509 SIUs
have separate data and instruction buses; the 800 and 555
devices combine these buses outside the SIU. The 800 family
has both instruction and data caches and an MMU. The
caches are two-way set-associative and feature lockability on
a line.
Special instructions: Motorola has expanded the PowerPC
architecture with its AltiVec technology—162 new instruc-
tions along with a 128-bit vector-execution unit that per-
forms single-instruction multiple-data operations concur-
rently with the integer units and FPUs. AltiVec supports
16-way parallelism for 8-bit integers and characters, eight-
way parallelism for 16-bit integers, and four-way parallelism
for 32-bit integers and IEEE floating-point numbers. AltiVec
also includes a separate register file with 32 128-bit-wide reg-
isters.
Development tools: The PowerPC families have a large
third-party tool-supplier base. IBM also offers development
tools for all its PowerPC embedded processors. These tools
include a C/C++ compiler; a RISCWatch debugger with in-cir-
cuit emulation; a ROM monitor; RTOS-aware debugging; and
real-time, noninvasive trace capability.
Second sources: Mitsubishi is a second source for IBM’s
embedded PowerPC mPs.
IBM/Motorola PowerPC (continued)
IBM/Motorola PowerPC (continued)
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