3/24/97 4-9 CPU Organization
Note that serial port buffers, PCA capture registers, and WatchDog feed registers (if present) are
unaffected. Consult the XA derivative data sheet for more information.
After the XA internal reset sequence has been completed, the device is quiescent until the RST
line goes high.
4.4.4 XA Configuration at Reset
As the
RST line goes high, the value on two input pins is sampled to determine the XA memory
and bus configuration. The
EA and BUSW pins (if present on a specific XA derivative) have
special function during the reset sequence, to allow external hardware to determine the use of
internal or external program memory, and to select the default external bus width.
Immediately after the
RST line goes high, the CPU triggers a reset exception interrupt, as
described in the next section.
Selecting Internal or External Program Memory
The XA is capable of reading instructions from internal or external memory, both of which may
be present. The XA
EA input pin determines whether internal or external program memory will
be used. The
EA pin is sampled on the rising edge of the RST pulse. If EA = 0, the XA will
operate out of external program memory, otherwise it will use internal code memory. The
selection of external or internal code memory is fixed until the next time
RST is asserted and
released; until then all code fetches will access the selected code memory.
The XA cannot detect inconsistencies between the setting detected on the EA input and the
hardware memory configuration. For example, setting
EA = 1 on a ROMless XA variant will
cause the XA to attempt to execute internal code memory, which is undefined on a ROMless
device, typically resulting in a system failure.
Selecting External Bus Width
The XA is capable of accessing an 8 or 16 bit external data bus. The BUSW pin tells the XA the
external data bus configuration. BUSW=0 selects an 8-bit bus and BUSW=1 selects an 16-bit
bus. On power-up, the XA defaults to the 16-bit bus (due to an on-chip weak pull-up on BUSW).
The BUSW pin is sampled on the rising edge of the
RST pulse. If BUSW is low, the XA
operates its external bus interface in 8 bit mode, otherwise, the XA uses 16 bit bus operation. The
bus width may also be set under software control on derivatives equipped with the BCR (“Bus
Configuration Register”) SFR.
After
RST is released, the BUSW pin may be used an alternate function on some XA derivatives.
Consult derivative data sheets for exact pinouts and details of how pins such as these may be
shared to keep package size small.
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