3/24/97 4-19 CPU Organization
Returns from all interrupts should in most cases be accomplished by the RETI instruction, which
pops the System Stack and continues execution with the restored PSW context. Since RETI
executed while in User Mode will result in an exception trap, as described further below,
interrupt service routines will normally be executed in System Mode.
The XA architecture contains sophisticated mechanisms for deciding when and if an interrupt
sequence actually occurs. As described below, Exception Interrupts are always serviced as soon
as they are triggered. Event Interrupts are deferred until their execution priority is higher than
that of the currently executing code. For both exception and event interrupts, there is a
systematic way of handling multiple simultaneous interrupts. Software and trap interrupts occur
only when program instructions generating them are executed so there is no need for conflict
resolution.
The Non-Maskable Interrupt requires special consideration. It is generated outside the XA core,
and in that respect is an event interrupt. However, it shares many characteristics of exception
interrupts, since it is not maskable. Note that NMI, while part of the XA CPU core, may not
always be connected to a pin or other event source on all XA derivatives.
4.8.1 Interrupt Type Detailed Descriptions
This section describes the four kinds of interrupts in detail.
Exception Interrupts
Exception interrupts reflect events of overriding importance and are always serviced when they
occur. Exceptions currently defined in the XA core include: Reset, Breakpoint, Divide-by-0,
Stack overflow, Return from Interrupt (RETI) executed in User Mode, and Trace. Nine
additional exception interrupts are reserved. NMI is listed in the table of exception interrupts
(Table 4.1) below because NMI is handled by the XA core in same manner as exceptions, and
factors into the precedence order of exception processing.
Since exception interrupts are by definition not maskable, they must always be serviced
immediately regardless of the priority level of currently executing code, as defined by the IM bits
in the PSW. In the unusual case that more than one exception is triggered at the same time, there
is a hard-wired service precedence ranking. This determines which exception vector is taken first
if multiple exceptions occur. In these cases, the exception vector taken last may be considered
the highest priority, since its code will execute first. Of course, being non-maskable, any
exception occurring during execution of the ISR for another exception will still be serviced
immediately.
Programmers should be aware of the following when writing exception handlers:
1. Since another exception could interrupt a stack overflow exception handler routine, care
should be taken in all exception handler code to minimize the possibility of a destructive stack
overflow. Remember that stack overflow exceptions only occur once as the stack crosses the
bottom address limit, 80h.
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