XA User Guide 4-18 3/24/97
These default stack pointer start-up values overlap the System and User stacks and are applicable
only when one of these stacks will never be used.
Since the System stack is used for all exception and interrupt processing, this may not be
appropriate in all XA applications. The startup code should normally set new and different
values of both USP and SSP.
4.8 XA Interrupts
The XA architecture defines four kinds of interrupts. These are listed below in order of intrinsic
priority:
• Exception Interrupts
• Event Interrupts
• Software Interrupts
• Trap Interrupts
Exception interrupts reflect system events of overriding importance. Examples are stack
overflow, divide-by-zero, and Non-Maskable Interrupt. Exceptions are always processed
immediately as they occur, regardless of the priority of currently executing code.
Event interrupts reflect less critical hardware events, such as a UART needing service or a timer
overflow. Event interrupts may be associated with some on-chip device or an external interrupt
input. Event interrupts are processed only when their priority is higher than that of currently
executing code. Event interrupt priorities are settable by software.
Software interrupts are an extension of event interrupts, but are caused by software setting a
request bit in an SFR. Software interrupts are also processed only when their priority is higher
than that of currently executing code. Software interrupt priorities are fixed at levels from 1
through 7.
Trap interrupts are processed as part of the execution of a TRAP instruction. So, the interrupt
vector is always taken when the instruction is executed.
All forms of interrupts trigger the same sequence: First, a stack frame containing the address of
the next instruction and then the current value of the PSW is pushed on the System Stack. A
vector containing a new PSW value and a new execution address is fetched from code memory.
The new PSW value entirely replaces the old, and execution continues at the new address, i.e., at
the specific interrupt handler.
The new PSW value may include a new setting of PSW bit SM, allowing handler routines to be
executed in System or User mode, and a new value of PSW bits IM3 through IM0, reflecting the
execution priority of the new task. These capabilities are basic to multi-tasking support on the
XA. See Chapter 5 for more details.
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