3/24/97 4-27 CPU Organization
One consequence of this sequence is that the instruction that sets TM = 1 cannot generate a
Trace, since TM is not latched when the instruction is actually executed. Another consequence is
that an instruction that generates an exception will never be traced. Finally if an event interrupt
occurs during an instruction clock when the instruction being executed is a TRAP, the TRAP
will be executed, then the trace service, and finally the interrupt will be serviced.
4.9.2 Trace Mode Initialization and Deactivation
Since PSW.TM is in the protected portion of the PSW (i.e., in PSWH), only code executing in
System Mode can initiate or turn off Trace Mode. In practice, this may be done by invoking a
trap whose replacement PSW clears this bit, or by executing a RETI instruction with a synthetic
Exception/Interrupt stack frame explicitly pushed on the top of the System Stack, as follows:
Tracing will continue until the PSW bit TM is cleared. This may be done by the trace service
routine by examining the stack frame at the top of the system stack and clearing the TM bit prior
to returning to the currently traced process. A similar method may be used to initiate trace mode.
Note that stack frames generated by exception interrupts are always placed on the System stack.
It is probably a good idea for the trace service routine to verify that the item in the stack frame is
consistent with the traced process before modifying the TM bit.
Figure 4.21 Instruction Execution Clock Detail
Instruction n
latch
TM
state
Y
instruction
allowed?
N
Instruction
illegal?
Execute
Instruction
service
exception
Check latch;
TM = 1?
Y
service
trace
Interrupt
pending?
Y
service
interrupt
PC (hi-byte)0x00
address of next instruction
TM set in saved PSW image
Lo-order 16-bits of PC
PSW
in traced routine
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