4/17/98 7-1 External Bus
7 External Bus
Most XA derivatives have the capability of accessing external code and/or data memory through
the use of an external bus. The external bus provides address information to external devices that
are to be accessed, then generates a strobe for the required operation, with data passing in or out
on the data bus. Typical bus operations are code read, data read, and data write. The standard XA
external bus is designed to provide flexibility, simplicity of connection, and optimization for
external code fetches.
The following discussion is based on the standard version of the XA external bus. Some specific
XA derivatives may have a different implementation of the external bus, or no external bus at all.
7.1 External Bus Signals
For flexibility, the standard XA external bus supports 8 or 16-bit data transfers and a user
selectable number of address bits. The maximum number of address lines varies by derivative
but may be up to 24. A standard set of bus control signals coordinates activity on the bus. These
are described in the following sections.
7.1.1
PSEN - Program Store Enable
The program store enable signal is used to activate an external code memory, such as an
EPROM. This active low signal is typically connected to the Output Enable (OE) pin of an
external EPROM.
PSEN remains high when a code read is not in progress.
7.1.2
RD - Read
The bus read signal is also active low. Activity of this signal indicates data read operations on the
external bus. RD is typically connected to the pin of the same name on an external peripheral
device.
7.1.3 WRL - Write Low Byte
WRL is the external bus data write strobe. It is typically connected to the WR pin of an external
peripheral device. When the XA external bus is used in the 16-bit mode, this strobe applies only
to the lower data byte, allowing byte writes on the 16-bit bus. The
WRL signal is active low.
7.1.4
WRH - Write High Byte
For a 16-bit data bus, a signal similar to
WRL, but for the upper data byte is needed. The active
low signal
WRH serves this purpose.
7.1.5 ALE - Address Latch Enable
Since a portion of the XA external bus is used for multiplexed address and data information, that
part of the address must be latched outside of the XA so that it will remain constant during the
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