4/17/98 7-7 External Bus
7.3 Bus Timing and Sequences
The standard XA external bus allows programming the widths of the bus control signals ALE,
PSEN, WRL, WRH, and RD. There is also an option to extend the data hold time after a write
operation. The combinations available will allow interfacing most devices to the XA directly
without the need for special buffers or a WAIT state generator. Note that there is always a "rest
clock" after any type of bus cycle except part of a burst mode code read. That is, when a bus
cycle is completed and the bus strobe de-asserted, no new bus cycle will be begun until one clock
has passed with no bus activity.
7.3.1 Code Memory
Interfacing with external code memory, typically in the form of EPROMs, is enabled by the
PSEN control signal. If the XA is configured to execute internal code memory at reset, by the
setting of the
EA pin, it will automatically begin to fetch external code if the program crosses the
boundary from internal to external code space. The location of this boundary varies for different
XA derivatives, depending on the size of the internal code memory for each part.
Since the XA employs a pre-fetch queue in order to optimize instruction execution times,
fetching of external instructions may begin before program execution actually crosses the on/off-
chip code memory boundary. If a branch or subroutine return is located near the end of on-chip
code memory, the off-chip fetch would be unnecessary, and may in fact cause problems if the
XA ports that implement the external bus are being used for other purposes. For this reason, the
BUSD (bus disable) bit in the Bus Configuration Register (BCR) is provided to prevent the XA
from using the external bus for code or data operations.
Note also that external code read cycles may sometimes be aborted by the XA. This happens
when a code pre-fetch is occurring on the bus and the XA must execute a branch. The instruction
data from the code pre-fetch will not be needed, so the bus cycle will be terminated immediately.
This may appear as an ALE with no subsequent PSEN strobe, or a PSEN strobe that is shorter
than that specified by the bus timing registers.
Code Read with ALE
The classic operation of a multiplexed address and data bus involves the issuance of an address,
along with its associated control signal, for every bus cycle. The XA uses the bus control signal
ALE to indicate that an address is on the bus that must be latched through the following code or
data operation. The following diagram shows a code memory fetch in a cycle using ALE.
Burst Code Read (No ALE)
The XA does not always require an ALE cycle for every code fetch. This feature is included
specifically to improve performance when the XA executes code from external memory, while
increasing the access time available for the external memory device. Because the lower four
address lines of the external bus are always driven, not multiplexed, the XA can access up to 16
bytes (or 8 words) of sequential code memory each time an ALE is issued. This type of fast
sequential code read is called a burst read. Of course, any type of jump, branch, interrupt, or
other change in sequential program flow will require an ALE in order to change the code fetch
address in a non-sequential manner. Any data operation (read or write) on the XA external bus
also requires an ALE cycle and will cause any subsequent external code fetch to begin with an
ALE cycle also.
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