Intel 8253 - Page 654

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FIGURE 28. MODE 1 (STROBED OUTPUT)
FIGURE 29. MODE 2 (BI-DIRECTIONAL)
NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF • MASK • STB • RD • OBF •
MASK • ACK • WR)
Timing Waveforms (Continued)
tWOB (21)
tWB (12)
tAK (15) tAIT (27)
tAOB (22)
tWIT
OBF
WR
INTR
ACK
OUTPUT
(28)
tWOB
tAOB
tAK
tAD (19)
tKD
tPH (18)
tPS (17)
tSIB
tST
OBF
WR
INTR
ACK
IBF
STB
PERIPHERAL
BUS
RD
tRIB (24)
DATA FROM
PERIPHERAL TO 82C55A
DATA FROM
82C55A TO PERIPHERAL
DATA FROM
82C55A TO CPU
DATA FROM
CPU TO 82C55A
(21)
(22)
(15)
(16)
(20)
(23)
(NOTE)
(NOTE)
82C55A