Understanding when the CPU recognizes different sorts of exceptions and interrupts will also
help you understand that there are actually very few exceptions that can occur truly
simultaneously. For instance, although there are a number of exceptions that the CPU detects
when it decodes an instruction, there is only one instruction at a time (ignoring pipelining). Thus,
you could never have a privilege violation and an unimplemented instruction at the same time.
Although bounds violations and zero divide exceptions both occur during the execute phase of
the fetch/execute cycle, it is impossible to be be both dividing and checking bounds
simultaneously. If we ignore pipelining, in fact, we can never have two software exceptions
occur at the same time unless one is a debug exception such as a trace. Finally, even though two
or more peripheral devices may assert an interrupt request simultaneously, the CPU will detect
only one of them, since the priority encoder ensures that only one interrupt request at a time will
reach the microprocessor.
Prioritizing exceptions
Even with the varying detection times for the different exceptions, certain exceptions can occur
simultaneously. For example, a trace exception and a peripheral device interrupt could occur
together, since the CPU detects both between instructions. In such a case, it is important to
understand what happens. First, not only is there a priority scheme that determines which
peripheral device interrupt will receive the CPU's attention first, there is also a priority scheme
that encompasses all exceptions and interrupts. You can find the priority scheme that appears
below on your reference card. You should also be aware that the INT instruction (not shown with
the other priorities) has higher priority than any other. This priority scheme is not so much meant
to rank exceptions in terms of "importance". Instead, the priorities are meant to ensure that the
behavior of the CPU is appropriate. In fact, it is probably more productive to imagine that a
higher priority means less important in most cases.
Priority Exception
Highest
Lowest
• trace
• breakpoint
• segment not present or general protection fault (for instructions)
• NMI
• maskable interrupt
• illegal instruction, privilege violation
• coprocessor not available
• segment not present, stack fault, general protection fault (for operands)
• alignment faults
• page faults
Note: These groups and priorities are listed on the back of your reference card just below the
Hardware Interrupt Assignment table on the center panel.
Examples of how two exceptions can occur at once:
1. a segment not present fault occurs during the operand fetch of an INT instruction (the
INT instruction has priority)
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