the "ticks" of the clock. The CPU recognizes an edge-sensitive interrupt only at the moment of
the transition from low to high voltage. Thus, the detection of this type of interrupt occurs within
one clock pulse of the moment it is asserted and does not occur again. This scheme prevents an
NMI from interrupting itself.
Edge-triggered interrupts
Multiple Simultaneous Exceptions
The discussion of interrupt requests and the response to them of the CPU is explains how a
processor can handle situations where more than one hardware device asserts an interrupt at the
same time. We also need to look at situations when other kinds of exceptions occur
simultaneously. First, we need to specify when the CPU recognizes the various types of
exceptions, since this determines what kinds of exceptions can occur at at the same time.
When the CPU Recognizes Various Kinds of Exceptions
Aside from remembering when the CPU detects hardware interrupts, you should not need to
memorize the times that the CPU recognizes software exceptions. If you realize that the CPU
will recognize an exception as soon as possible, you should be able to determine when it will
recognize a particular exception, just by reasoning about it. As a result, you should look at the
software exceptions in the following list as a means of testing your own reasoning, rather than as
a rote-learning task. It is also important to remember that ultimately, the CPU will recognize any
exception or interrupt at an instruction boundary (that is, between instructions). This is because
the occurrence of a software exception aborts any remaining steps in the fetch/execute cycle.
1. The CPU recognizes nonmaskable interrupts as soon as it detects the signal, as detailed
above.
2. The CPU recognizes peripheral device interrupts only between instructions.
3. The CPU recognizes bus and address errors such as faults or nonexistent addresses
immediately. Since they usually occur during (and as a result of) instruction execution
and since they make it impossible to complete execution of the current instruction, this
makes perfect sense. These exceptions can occur any time the CPU reads from or writes
to memory, so they may occur when the microprocessor fetches an instruction or an
operand or when it writes a result back to memory.
4. The CPU recognizes privilege violations, the INT and INTO instructions and illegal or
unimplemented instructions as soon as the it decodes the instruction, which is the same as
saying that it recognizes them as soon as it detects them.
5. The CPU recognizes a zero divide exception during the execute phase of the divide
instruction.
6. The CPU detects trace and other debug exceptions between instructions.
7. The CPU detects bounds violations during the execute phase of the BOUND instruction.
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