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Intel 8253 - Page 747

Intel 8253
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disconnected)
SR3 (CTS) Clear to Send--set by modem
SR4 (FE) Framing Error--set when a character was not properly preceded and followed
by a start and/or stop bits, which indicates an error in transmission of some
kind
SR5 (OVRN) OVerRuN--data was lost, that is, it was received but the CPU did not read it
before it was overwritten
SR6 (PE) parity error
SR7 (IRQ) Interrupt ReQuest pending--cleared by a read from the RDR or a write to the
TDR
The interrupt service routine uses information from the status register to determine what to do.
For example, if the ACIA has set SR0, then an interrupt is a request for the interrupt service
routine to read data. If the ACIA has set SR1, then an interrupt is a request for the handler to
write data. Note that other services may be necessary for error recovery, as indicated by other
bits in the SR.
References
Eggebrecht, L.C. Interfacing to the IBM Personal Computer. Indianapolis: Howard W. Sams and
Co. 1983.
Ford, William and William Topp. Assembly Language and Systems Programming for the
M68000 Family (Second Ed.). Lexington, MA: D.C. Heath, 1992.
Intel. i486 Microprocessor: Hardware Reference Manual. Intel Corporation, 1990.
86/88, 186/188 User's Manual: Programmer's Reference. Intel Corporation, 1985.
Intel486™ Microprocessor Family: Programmer's Reference Manual. Intel Corporation, 1992.
Intel. Microprocessor and Peripheral Handbook. Intel Corporation, 1983.
IBM. IBM BIOS Technical Reference. International Business Machines Corporation, 1984.
Motorola. M68000 8-/16-/32-Bit Microprocessors: User's Manual (Sixth Ed.). Englewood
Cliffs, NJ: Prentice Hall, 1989.
Motorola. Data Sheet for MC6850, MC68A50 and MC68B50, 1978.
Orejel, Jorge. Personal Communication.
Wakerly, John. Microcomputer Architecture and Programming: The 68000 Family. NY: Wiley,
1989.

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