Lattice Semiconductor CertusPro-NX - Page 120

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
120 © 2020-2021 Lattice Semiconductor FPGA-TN-02245-0.81
All rights reserved. CONFIDENTIAL
Primitive Ports
MPCS Foundational IP Port –
MPCS/EPCS
MPCS Foundational IP Port – PIPE
CH[3:0]_PIPE_RXEQ_DIR_PCS_RX_FIFO_ST
mpcs_rx_fifo_st_o[3:2]
pipe_rxeq_dir_pcs_rx_fifo_st_o
CH[3:0]_PCS_RX_HI_BER
mpcs_rx_hi_ber_o
—
CH[3:0]_PCS_RX_BLK_LOCK
mpcs_rx_blk_lock_o
—
CH[3:0]_PCS_TX_FIFO_ST
mpcs_tx_fifo_st_o[3:2]
—
CH[3:0]_ PIPE_TX_DATA_EN
mpcs_tx_fifo_st_o[1]
pipe_tx_data_en_o
CH[3:0]_ PIPE_LOCAL_GET_TX_COEF_VLD
mpcs_tx_fifo_st_o[0]
pipe_local_get_tx_coef_vld_o
CH[3:0]_PIPE_WIDTH_2G5_LL
—
pipe_width_2g5_LL_o
CH[3:0]_PIPE_WIDTH_5G0_LL
—
pipe_width_5g0_LL_o
CH[3:0]_PIPE_WIDTH_8G0_LL
—
pipe_width_8g0_LL_o
CH[3:0]_PIPE_POWER_DOWN_LL
—
pipe_power_down_LL_i
CH[3:0]_PIPE_RATE_LL
—
pipe_rate_LL_i
CH[3:0]_PIPE_TX_DETECT_RX_LOOPBACK_LL
—
pipe_tx_detect_rx_loopback_LL_i
CH[3:0]_PIPE_RX_EQ_EVAL_LL
—
pipe_rx_eq_eval_LL_i
CH[3:0]_PIPE_INVALID_REQUEST_LL
—
pipe_invalid_request_LL_i
CH[3:0]_PIPE_RX_EQ_EVAL_FEEDBACK_FOM_LL
—
pipe_rx_eq_eval_feedback_fom_LL_o
CH[3:0]_PIPE_RX_EQ_EVAL_FEEDBACK_DIR_LL
—
pipe_rx_eq_eval_feedback_dir_LL_o
CH[3:0]_PIPE_RX_PRESET_HINT_ENABLE_LL
—
1’b0
CH[3:0]_PIPE_RX_PRESET_HINT_LL
—
pipe_rx_preset_hint_LL_i
CH[3:0]_PIPE_PHY_STATUS_LL
—
pipe_phy_status_LL_o
CH[3:0]_PIPE_RX_POLARITY_LL
—
pipe_rx_polarity_LL_i
CH[3:0]_PIPE_RX_ELEC_IDLE_LL
—
pipe_rx_elec_idle_LL_o
CH[3:0]_PIPE_RX_CLKREQ_N_LL
—
pipe_rx_clkreq_n_LL_o
CH[3:0]_PIPE_TX_CLKREQ_N_LL
—
pipe_tx_clkreq_n_LL_i
CH[3:0]_PIPE_TX_CM_DISABLE_LL
—
pipe_tx_cm_disable_LL_i
CH[3:0]_PIPE_RX_EI_DISABLE_LL
—
pipe_rx_ei_disable_LL_i
CH[3:0]_PIPE_L1PMSSEN_LL
—
1’b0
CH[3:0]_PIPE_TX_SWING_LL
—
pipe_tx_swing_LL_i
CH[3:0]_PIPE_TX_MARGIN_LL
—
pipe_tx_margin_LL_i
CH[3:0]_PIPE_TX_DEEMPH_LL
—
pipe_tx_deemph_LL_i
CH[3:0]_PIPE_TX_DEEMPH_WINDOW_LL
—
1’b0
CH[3:0]_PIPE_LOCAL_FS_LL
—
pipe_local_fs_LL_o
CH[3:0]_PIPE_LOCAL_LF_LL
—
pipe_local_lf_LL_o
CH[3:0]_PIPE_LOCAL_GET_PRESET_COEF_LL
—
pipe_local_get_preset_coef_LL_i
CH[3:0]_PIPE_LOCAL_GET_PRESET_INDEX_LL
—
pipe_local_get_preset_index_LL_i
CH[3:0]_PIPE_LOCAL_GET_TX_COEF_VALID_LL
—
pipe_local_get_tx_coef_valid_LL_o
CH[3:0]_PIPE_LOCAL_GET_TX_PRESET_COEF_LL
—
pipe_local_get_tx_preset_coef_LL_o
CH[3:0]_PIPE_REMOTE_FS_LL
—
6’b0
CH[3:0]_PIPE_REMOTE_LF_LL
—
6’b0
CH[3:0]_PIPE_REMOTE_EQ_RX_DEEMPH_LL
—
18’b0
CH[3:0]_PIPE_REMOTE_EQ_RX_PRESET_LL
—
4’b0
CH[3:0]_PIPE_TX_DATA_ENABLE_LL
—
pipe_tx_data_enable_LL_o
CH[3:0]_PIPE_TX_DATA_VALID_LL
—
pipe_tx_data_valid_LL_i
CH[3:0]_PIPE_TX_START_BLOCK_LL
—
pipe_tx_start_block_LL_i
CH[3:0]_PIPE_TX_SYNC_HEADER_LL
—
pipe_tx_sync_header_LL_i
CH[3:0]_PIPE_TX_DATA_LL
—
pipe_tx_data_LL_i
CH[3:0]_PIPE_TX_DATAK_LL
—
pipe_tx_datak_LL_i
CH[3:0]_PIPE_TX_COMPLIANCE_LL
—
pipe_tx_compliance_LL_i