Lattice Semiconductor CertusPro-NX Usage Guide

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
32 © 2020-2021 Lattice Semiconductor FPGA-TN-02245-0.81
All rights reserved. CONFIDENTIAL
Port Name
I/O
Width
Description
2’b00 – Gen1
pipe_powerdown_i
In
2*NL
Powerdown. This is a per-lane signal.
pipe_powerdown_i[1:0] = power state driving by the
PCI-Express controller:
2’b11 – P2
2’b10 – P1
2’b01 – P0s
2’b00 – P0
pipe_phy_status_o
Out
NL
This signal is a per-lane signal which is generated by the PHY
macro for each lane of the PCI-Express controller.
pipe_txdetectrx_i
In
NL
TxdetectRx/Loopback. This signal is a per-link signal which is
generated by each link PCI-Express controller. The PCS logic
performs the internal mapping of link to lanes.
pipe_txdeemp_i
In
18*NL
Transmit de-emphasis. This signal is a per-link signal which is
generated by each link PCI-Express controller. The PCS logic
performs the internal mapping of link to lanes.
pipe_txmargin_i
In
3*NL
Transmit margin. This signal is used at 5 Gbps or 8 Gbps speed
by the MAC in order to control the PHY settings in term of
amplitude, de-emphasis. This signal is a per-link signal which is
generated by each link PCI-Express controller. The PCS logic
performs the internal mapping of link to lanes.
pipe_tx_swing_i
In
NL
Transmit swing. This signal is a per-link signal which is generated
by each link PCI-Express controller. The PCS logic performs the
internal mapping of link to lanes.
pipe_txdata_i
In
32*NL
Transmit data. CI-Express controller. The width of this signal can
be 8 bits or 16 bits per lane depending on whether PIPE16BIT is
defined or not.
pipe_txdatak_i
In
4*NL
Transmit control character. This signal is a per-lane signal. The
width of this signal can be 1 bit, 2 bits or 4 bits per lane,
depending on whether PIPE16BIT or PIPE32BIT is defined or not.
pipe_txdatavalid_i
In
NL
Transmit data valid. The PCS logic performs the internal
mapping of link to lanes
pipe_tx_start_block_i
In
NL
Transmit data starting byte.
pipe_txsyncheader_i
In
2*NL
Transmit sync header.
pipe_tx_elec_idle_i
In
NL
Transmit electrical idle. This signal is a per-lane signal which is
generated by each link PCI-Express controller.
pipe_txcompl_i
In
NL
Transmit compliance. This signal is a per-lane signal which is
generated by each link PCI-Express controller.
pipe_rxdata_o
Out
32*NL
Receive data. This signal is a per-lane signal which is generated
by the PHY macro for the PCI-Express controller. The width of
this signal can be 8 bits, 16 bits or 32 bits per lane, depending
on whether PIPE16BIT or PIPE32BIT is defined or not.
pipe_rxdatak_o
Out
4*NL
Receive control character. This signal is a per-lane signal which
is generated by the PCI-Express PHY for the PCI-Express
controller. The width of this signal can be 1 bit, 2 bits or 4 bits
per lane, depending on whether PIPE16BIT or PIPE32BIT is
defined or not.
pipe_rxdatavalid_o
Out
NL
Receive data valid. This signal is a per-lane signal which is
generated by the PHY macro for the PCI-Express controller.
pipe_rx_start_block_o
Out
NL
Receive data starting byte. This signal allows the PHY to tell the
MAC the starting byte for 128-bit block. This signal is a per-lane
signal which is generated by the PHY macro for the PCI-Express
controller.
pipe_rxsyncheader_o
Out
NL
Receive sync header bits. This signal reports the content of the

Lattice Semiconductor CertusPro-NX Specifications

General

Brand	Lattice Semiconductor
Model	CertusPro-NX
Category	Computer Hardware
Language	English