Lattice Semiconductor CertusPro-NX Usage Guide

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
FPGA-TN-02245-0.81 © 2020-2021 Lattice Semiconductor 33
All rights reserved. CONFIDENTIAL
Port Name
I/O
Width
Description
sync header bits of the 130-bit block. This signal is only valid
when both pipe_rxdatavalid_o and pipe_rx_start_block_o are
asserted. This signal is a per-lane signal which is generated by
the PHY macro for the PCI-Express controller.
pipe_rx_elec_idle_o
Out
NL
This port is used to signal the Electrical Idle condition detected
by the PMA control logic.
pipe_rxval_i
Out
NL
This signal is used to signal receive valid data.
pipe_rx_polarity_i
In
NL
Receive polarity. This signal is a per-lane signal which is
generated by each link PCI-Express controller.
pipe_rxstatus_o
Out
3*NL
Receive status. This signal is a per-lane signal which is generated
by the PCI-Express PHY in order to report specific status such as
receiver detected, 128 bits or 130 bits code or disparity error at
8 Gbps, 128 bits or 130 bits code or disparity error at 2.5 Gbps
or 5 Gbps, Elastic buffer underflow/overflow/SKIP added or SKIP
removed.
pipe_blockalignctrl_i
In
NL
Block align control. This signal is a per-lane signal which is set by
the MAC layer in order to allow the PHY to align on EIEOS in
gen3 data rate. When clear, the PHY keeps the current
alignment of its received gearbox.
PIPE Transmitter Control for Remote RxEQ Evaluation
pipe_local_fs_o
Out
6*NL
Local Full Swing (FS). This signal is a per-lane signal which
reports to the MAC layer the local FS. This signal is always set to
32 by the PHY for each lane.
pipe_local_lf_o
Out
6*NL
Local FS. This signal is a per-lane signal which reports to the
MAC layer the local Low Frequency (LF). This signal is always set
to 10 by the PHY for each lane.
pipe_local_get_preset_coef_i
In
NL
Get local preset mapping to coefficient. This signal is a per-lane
signal which is used by the MAC layer to get the coefficient
corresponding to the preset giving on the
pipe_local_get_preset_index_i [3:0] signal of each lane.
pipe_local_get_preset_index_i
In
4*NL
Local preset index. This signal is a per-lane signal which is used
by the MAC layer to indicate the coefficient the MAC asks to get
the coefficient mapping.
pipe_local_get_tx_coef_valid_o
Out
NL
Local Tx coefficient valid. This signal is a per-lane signal which is
used by the PHY layer to indicate the required preset to
coefficient mapping is valid on
pipe_local_get_tx_preset_coef_o[17:0] output signal.
pipe_local_get_tx_preset_coef_o
Out
18*NL
Local Tx coefficient mapping. This signal is a per-lane signal
which is used by the PHY layer to indicate the coefficient value
corresponding to the required preset.
PIPE RxEQ Evaluation
pipe_rxeqeval_i
In
NL
Rx equalization evaluation request. This signal is a per-lane
signal which is used by the MAC layer to request a receiver
equalization evaluation.
pipe_invalidrequest_i
In
NL
Rx equalization invalid request. This signal is a per-lane signal
which is used by the MAC layer to report to the PHY that the
link partner has indicated an invalid request. The invalid request
indicates the transmit coefficient and the link partner is not able
to apply.
pipe_rxpresethint_i
In
3*NL
Rx equalization preset hint. This signal is a per-lane signal which
is used by the MAC layer to indicate to the PHY a good starting
point for performing the first receiver equalization immediately
after entering gen3 data rate in order to achieve 10-4 BER. This
preset hint is used by the PHY as an initial value for CTLE gain,
but the PHY might iterate and try to find better initial value

Lattice Semiconductor CertusPro-NX Specifications

General

Brand	Lattice Semiconductor
Model	CertusPro-NX
Category	Computer Hardware
Language	English