CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
36 © 2020-2021 Lattice Semiconductor FPGA-TN-02245-0.81
All rights reserved. CONFIDENTIAL
PIPE Tx electrical idle.
1’b1 – Idle.
1’b0 – Active.
pipe_block_align_control_LL_i
PIPE block align control.
1’b1 – Allows the PHY to align on EIEOS in Gen3 data rate.
1’b0 – PHY keeps the current alignment of the Rx gearbox.
Width of pipe_tx_data_LL_i/pipe_rx_data_LL_o at 2.5G speed.
2’b11 – Reserved.
2’b10 – 32 bits.
2’b01 – 16 bits.
2’b00 – 8 bits.
Must be <= PHY_DATA_WIDTH. 2-bits only for >= 32-bit
PHY_DATA_WIDTH.
Width of pipe_tx_data_LL_i/pipe_rx_data_LL_o at 5.0G speed.
2’b11 – Reserved.
2’b10 – 32 bits.
2’b01 – 16 bits.
2’b00 – 8 bits.
Must be <= PHY_DATA_WIDTH. 2-bits only for >= 32-bit
PHY_DATA_WIDTH.
Width of pipe_tx_data_LL_i/pipe_rx_data_LL_o at 8.0G speed.
2’b11 – Reserved.
2’b10 – 32 bits.
2’b01 – 16 bits
2’b00 – 8 bits.
Must be <= PHY_DATA_WIDTH. 2-bits only for >= 32-bit
PHY_DATA_WIDTH.
pipe_rx_eq_eval_feedback_fom_LL_o
Refer to the pipe_linkevalfigure_o signal.
pipe_rx_eq_eval_feedback_dir_LL_o
Refer to the pipe_linkevalchange_o signal.
Set to 1 by PHY for one clock to communicate with PCS about Tx
detection, rate change, power down change, and equalization
evaluation completion.
PIPE Rx electrical idle.
1’b1 – Idle.
1’b0 – Active.
Open drain CLKREQ# pin input. Current value of open drain
CLKREQ# pin.
1’b1 – Request to disable PCIe reference clock.
1’b0 – Request to enable PCIe reference clock.
Local PHY FS value. Captured on first pipe_phy_status_LL_o ==
1’b1 after reset deassertion.
Local PHY LF value. Captured on first pipe_phy_status_LL_o ==
1’b1 after reset deassertion.
pipe_local_get_tx_coef_valid_LL_o
pipe_local_get_tx_preset_coef_LL_o
PIPE Tx data enable.
1’b1 – Tx Data is taken by PHY.
1’b0 – Tx Data output holds the value.
PIPE Rx data enable.
1’b1 – Data is provided by PHY.
1’b0 – Rx Data input is unused.
PIPE Rx Data Valid for >= 8G only.
To Next Page
Loading...