Lattice Semiconductor CertusPro-NX Usage Guide

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
FPGA-TN-02245-0.81 © 2020-2021 Lattice Semiconductor 35
All rights reserved. CONFIDENTIAL
Port Name
I/O
Width
Description
for performing the first receiver equalization immediately after
entering Gen3 data rate in order to achieve 10
-4
bit error ratio.
This preset hint is used by the PHY as an initial value for CTLE
gain, but the PHY might iterate and try to find better initial
value which can enable to properly lock the CDR and reach a
valid state of receiver adaptation.
pipe_rx_polarity_LL_i
In
NL
Receive polarity:
1'b1 – Normal.
1'b0 – Inversed.
pipe_tx_clkreq_n_LL_i
In
NL
Open drain CLKREQ# pin output.
1’b1 – Drive CLKREQ# pin High-Z.
1’b0 – Drive CLKREQ# pin low to enable PCIe reference clock.
pipe_tx_cm_disable_LL_i
In
NL
TX Common Mode disable.
1’b1 – PHY is permitted to disable TX Common Mode
management.
1’b0 – PHY is not permitted to disable TX Common Mode
management.
pipe_rx_ei_disable_LL_i
In
NL
RX electrical idle disable.
1’b1 – PHY is permitted to disable Electrical Idle detection.
1’b0 – PHY is not permitted to disable Electrical Idle
detection.
pipe_tx_swing_LL_i
In
NL
2.5G/5G transmitter amplitude:
1’b1 – Reduced Swing.
1’b0 – Full Swing.
pipe_tx_margin_LL_i
In
3*NL
Transmitter test amplitude selection. Used for test only.
3’h0 – Normal operation.
pipe_tx_deemph_LL_i
In
18*NL
Per lane transmitter de-emphasis.
2.5G:(1==-3.5dB).
5G:(1==-3.5dB,0==-6dB).
8G:([17:12]==Post-Cursor,[11:6]==Cursor,[5:0]==Pre-Cursor).
pipe_local_get_preset_coef_LL_i
In
NL
Refer to the description of the pipe_local_get_preset_coef_i
signal.
pipe_local_get_preset_index_LL_i
In
4*NL
Refer to the description of the pipe_local_get_preset_index _i
signal.
pipe_tx_data_valid_LL_i
In
NL
PIPE Tx Data Valid for >= 8G only.
1’b1 – Data is valid.
1’b0 – Data is invalid.
De-asserted only to compensate for 128b130b encoding.
pipe_tx_start_block_LL_i
In
NL
PIPE Tx start block.
1’b1 – Start of block.
1’b0 – Otherwise.
All blocks transmitted are 128-bit.
pipe_tx_sync_header_LL_i
In
2*NL
PIPE Tx sync header.
When pipe_tx_start_block_LL_i == 1’b1, it indicates the block
type:
2’b01 – Ordered set.
2’b10 – Data.
pipe_tx_data_LL_i
In
32*NL
PIPE Tx Data.
pipe_tx_datak_LL_i
In
4*NL
PIPE Tx data K indicator for 8b10b.
pipe_tx_compliance_LL_i
In
NL
PIPE Tx compliance.
1’b1 – Force disparity to be negative before encoding
pipe_tx_data[7:0] (for 8b10b compliance pattern).
1’b0 – Normal operation.

Lattice Semiconductor CertusPro-NX Specifications

General

Brand	Lattice Semiconductor
Model	CertusPro-NX
Category	Computer Hardware
Language	English