Lattice Semiconductor CertusPro-NX - Page 5

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
FPGA-TN-02245-0.81 © 2020-2021 Lattice Semiconductor 5
All rights reserved. CONFIDENTIAL
Figures
Figure 5.1. CertusPro-NX 100k Device Block Diagram ........................................................................................................ 18
Figure 5.2. CertusPro-NX SerDes/PCS Quad Architecture .................................................................................................. 20
Figure 5.3. PCI Express Hard IP Architecture ...................................................................................................................... 21
Figure 5.4. PCI Express Link Layer Functional Diagram ....................................................................................................... 22
Figure 5.5. MPCS Quad Block Diagram ............................................................................................................................... 22
Figure 5.6. MPCS Channel Functional Block Diagram ......................................................................................................... 23
Figure 5.7. CertusPro-NX 100k Device SerDes Reference Clock Architecture .................................................................... 24
Figure 5.8. PCI Express Hard IP Mode ................................................................................................................................. 25
Figure 5.9. PIPE Mode ......................................................................................................................................................... 26
Figure 5.10. MPCS Mode .................................................................................................................................................... 26
Figure 5.11. PMA Only Mode .............................................................................................................................................. 27
Figure 5.12. Detailed Channel Block Diagram of MPCS-8B/10B Mode .............................................................................. 45
Figure 5.13. Detailed Channel Block Diagram of MPCS-64B/66B Mode ............................................................................ 45
Figure 5.14. Detailed Channel Block Diagram of MPCS-PMA Only Mode .......................................................................... 46
Figure 6.1. Simplified Block Diagram of the SerDes (PMA) ................................................................................................ 47
Figure 6.2. PCI Express AC Coupling Capacitors Location ................................................................................................... 48
Figure 6.3. PMA Controller Block Diagram ......................................................................................................................... 49
Figure 6.4. PCI Express PCS & PMA Controller Block Diagram ........................................................................................... 50
Figure 6.5. MPCS 8B/10B PCS Block Diagram ..................................................................................................................... 50
Figure 6.6. Tx Gearing Case I ............................................................................................................................................... 53
Figure 6.7. Tx Gearing Case II .............................................................................................................................................. 54
Figure 6.8. Rx Gearing Case I .............................................................................................................................................. 54
Figure 6.9. Rx Gearing Case II ............................................................................................................................................. 55
Figure 6.10. Byte Shifting for Word Alignment Pattern ...................................................................................................... 55
Figure 6.11. Word Aligner Block Diagram ........................................................................................................................... 57
Figure 6.12. Link Synchronization FSM ............................................................................................................................... 58
Figure 6.13. Before 2-byte Boundary Alignment ................................................................................................................ 59
Figure 6.14. After 2-byte Boundary Alignment................................................................................................................... 59
Figure 6.15. Data Stream before Word Alignment ............................................................................................................. 60
Figure 6.16. Data Stream after Word Alignment ................................................................................................................ 60
Figure 6.17. Bit Mapping of Input Data .............................................................................................................................. 60
Figure 6.18. The Expected Location of Synchronization Code ............................................................................................ 61
Figure 6.19. SKIP Pattern Format ........................................................................................................................................ 61
Figure 6.20. SKIP Pattern Mask Code ................................................................................................................................. 62
Figure 6.21. FIFO High/Low Water Line .............................................................................................................................. 62
Figure 6.22. Lane Alignment Pattern Mask Code ............................................................................................................... 63
Figure 6.23. Data Shifting for Alignment ............................................................................................................................ 63
Figure 6.24. 64B/66B PCS Channel Block Diagram ............................................................................................................. 64
Figure 6.25. XGMII vs. MPCS-Fabric Interface .................................................................................................................... 65
Figure 6.26. 64B/66B PCS Tx FIFO Write Operation Case I ................................................................................................. 66
Figure 6.27. 64B/66B PCS Tx FIFO Write Operation Case II ................................................................................................ 67
Figure 6.28. 64B/66B PCS Rx FIFO Read Operation Case I .................................................................................................. 67
Figure 6.29. 64B/66B PCS Rx FIFO Read Operation Case II ................................................................................................. 67
Figure 6.30. PMA Only Mode Block Diagram ...................................................................................................................... 69
Figure 6.31. Quad Reference Clock Source ......................................................................................................................... 71
Figure 7.1. 8B/10B PCS Channel Clock Diagram ................................................................................................................. 72
Figure 7.2. 64B/66B PCS Channel Clock Diagram ............................................................................................................... 73
Figure 7.3. PMA Only Mode Clock Diagram ........................................................................................................................ 75
Figure 7.4. Quad Clock Distribution Diagram ..................................................................................................................... 76
Figure 7.5. Two Quads Clock Connection ........................................................................................................................... 77
Figure 7.6. Single Quad Clock Connection .......................................................................................................................... 78
Figure 7.7. Case I-a Clock Structure .................................................................................................................................... 79