Lattice Semiconductor CertusPro-NX Usage Guide

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
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Figure 7.8. Case I-b Clock Structure .................................................................................................................................... 79
Figure 7.9. Case II-a Clock Structure ................................................................................................................................... 80
Figure 7.10. Case II-b Clock Structure ................................................................................................................................. 80
Figure 7.11. Case II-c Clock Structure ................................................................................................................................. 80
Figure 7.12. Case III-a Clock Structure ................................................................................................................................ 81
Figure 7.13. Case IV-a Clock Structure ................................................................................................................................ 82
Figure 7.14. Case IV-b Clock Structure ................................................................................................................................ 83
Figure 7.15. 64B/66B PCS with Using GPLL ......................................................................................................................... 84
Figure 7.16. 64B/66B PCS without using GPLL (Case I) ....................................................................................................... 84
Figure 7.17. 64B/66B PCS without Using GPLL (Case II) ..................................................................................................... 85
Figure 7.18. MPCS Mode Reset Sequence (Tx Path) ........................................................................................................... 87
Figure 7.19. MPCS Mode Reset Sequence (Rx Path)........................................................................................................... 87
Figure 7.20. EPCS Mode Reset Sequence (Tx Path) ............................................................................................................ 88
Figure 7.21. EPCS Mode Reset Sequence (Rx Path) ............................................................................................................ 88
Figure 8.1. Signal Distortion for Typical Backplane Application ......................................................................................... 89
Figure 8.2. Typical Backplane Application with Tx Equalizer .............................................................................................. 89
Figure 8.3. Typical Backplane Application with Rx Equalizer .............................................................................................. 90
Figure 8.4. Transmit Equalizer Block Diagram .................................................................................................................... 90
Figure 8.5. Definition of Tx Voltage Levels.......................................................................................................................... 91
Figure 8.6. Receive Equalizer Block Diagram ...................................................................................................................... 92
Figure 9.1. PMA Loopback Mode ........................................................................................................................................ 93
Figure 9.2. 8B/10B PCS Near-End Parallel Loopback Mode ................................................................................................ 94
Figure 9.3. 8B/10B PCS Far-End Parallel Loopback Mode ................................................................................................... 94
Figure 9.4. 64B/66B PCS Loopback Mode ........................................................................................................................... 95
Figure 9.5. Signal Detector .................................................................................................................................................. 95
Figure 9.6. CDR PLL Locking Flow ........................................................................................................................................ 96
Figure 10.1. Burst Read Transaction ................................................................................................................................... 98
Figure 10.2. Back-to-Back Read and Write Transaction...................................................................................................... 98
Figure 10.3. Back-to-Back Write and Read Transaction...................................................................................................... 99
Figure 13.1. Example Connection to Analog Power and Reference Pins .......................................................................... 107
Figure 14.1. MPCS Configuration GUI ............................................................................................................................... 110
Tables
Table 4.1. Standards Supported by the SerDes/PCS ........................................................................................................... 17
Table 5.1. Maximum Number of SerDes/PCS Channels per CertusPro-NX Device ............................................................. 19
Table 5.2. Maximum Number of PCI Express Blocks per CertusPro-NX Device .................................................................. 19
Table 5.3. Block Usage for the Corresponding SerDes/PCS Mode ...................................................................................... 20
Table 5.4. PCI Express Link Layer Quad Lane Mapping ....................................................................................................... 21
Table 5.5. 10GBASE-R Lane Mapping .................................................................................................................................. 24
Table 5.6. CertusPro-NX Mixed Protocols within a Quad ................................................................................................... 25
Table 5.7. MPCS Interface ................................................................................................................................................... 27
Table 5.8. EPCS Interface .................................................................................................................................................... 30
Table 5.9. PIPE Interface ..................................................................................................................................................... 31
Table 5.10. LMMI Interface ................................................................................................................................................. 37
Table 5.11. Other Signals .................................................................................................................................................... 38
Table 5.12. Data Bus Sharing and Mapping ........................................................................................................................ 39
Table 5.13. Control and Status Signals Functions (8B/10B PCS) ......................................................................................... 43
Table 5.14. Control and Status Signals Functions (64B/66B PCS) ....................................................................................... 43
Table 6.1. Operation Range for F
Ref
, F
VCO
, F
bit
, and F
PMA
...................................................................................................... 48
Table 6.2. Bit Mapping of Tx Data Bus ................................................................................................................................ 51
Table 6.3. Bit Mapping of Rx Data Bus ................................................................................................................................ 52

Lattice Semiconductor CertusPro-NX Specifications

General

Brand	Lattice Semiconductor
Model	CertusPro-NX
Category	Computer Hardware
Language	English