Lattice Semiconductor CertusPro-NX - Page 7

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
FPGA-TN-02245-0.81 © 2020-2021 Lattice Semiconductor 7
All rights reserved. CONFIDENTIAL
Table 6.4. Tx FIFO Usage ..................................................................................................................................................... 54
Table 6.5. Disparity Combinations ...................................................................................................................................... 55
Table 6.6. Example Settings for XAUI and GigE .................................................................................................................. 58
Table 6.7. PMA Only Mode Data Bus .................................................................................................................................. 69
Table 6.8. Channel Alignment within One Quad ................................................................................................................ 70
Table 6.9. Channel Alignment between Two Quads ........................................................................................................... 70
Table 7.1. 8B/10B PCS Channel Clock ................................................................................................................................. 72
Table 7.2. 64B/66B PCS Channel Clock ............................................................................................................................... 74
Table 7.3. PMA Only Mode Channel Clock ......................................................................................................................... 75
Table 7.4. Quad Clock ......................................................................................................................................................... 77
Table 7.5. Recommend Settings for Some Protocols.......................................................................................................... 78
Table 7.6. Reset and Power Control Signals ....................................................................................................................... 85
Table 8.1. Description of Tx Voltage Levels ........................................................................................................................ 90
Table 8.2. PCIe Tx Preset Ratios and Corresponding Coefficient Values ............................................................................ 91
Table 9.1. Loss of Signal Conditions .................................................................................................................................... 96
Table 9.2. Typical Duration Time for Each Lock Step .......................................................................................................... 96
Table 10.1. Access Type Definition ..................................................................................................................................... 99
Table 11.1. PCI Express Recommend AC Capacitance ...................................................................................................... 100
Table 11.2. GigE Configuration and IDLE Ordered Sets Definition ................................................................................... 102
Table 11.3. XAUI IDLE Ordered Sets Definition ................................................................................................................. 102
Table 11.4. 64B/66B Blocks Formats ................................................................................................................................ 103
Table 11.5. SLVS-EC Baud Rate ......................................................................................................................................... 103
Table 11.6. General Parameters of Receiver Characteristics for SLVS-EC ........................................................................ 104
Table 11.7. DisplayPort Recommend AC Capacitance ...................................................................................................... 104
Table 12.1. Transmit/Receive SerDes/PCS Latency .......................................................................................................... 105
Table 13.1. Recommended External Reference Resistor for Serval Differential Impedance Applications ....................... 107
Table 13.2. PCSREFMUX Usage ......................................................................................................................................... 107
Table 13.3. SerDes Power Pins Numbering ...................................................................................................................... 109
Table 13.4. Electrical Idle Related Signals ......................................................................................................................... 109
Table 14.1. Protocol Descriptions ..................................................................................................................................... 110
Table 14.2. Attributes Summary ....................................................................................................................................... 111
Table 14.3. Attributes Descriptions .................................................................................................................................. 115
Table 14.4. Pin-to-Pin Connection .................................................................................................................................... 117
Table A. 1. Register Address ............................................................................................................................................. 122
Table A. 2. Control Register 0 [reg00] ............................................................................................................................... 122
Table A. 3. Clock Count for Error Counter Decrement [reg01] ......................................................................................... 123
Table A. 4. Error Counter Threshold – Rx Idle Detect Max Latency [reg02] ..................................................................... 123
Table A. 5. Rx Impedance Ratio [reg03] ............................................................................................................................ 123
Table A. 6. Tx PLL F Settings and PCLK Ratio [reg04] ........................................................................................................ 123
Table A. 7. Tx PLL M & N Settings [reg05] ........................................................................................................................ 124
Table A. 8. Rx PLL F Settings and PCLK Ratio [reg06] ........................................................................................................ 124
Table A. 9. Rx PLL M & N Settings [reg07] ........................................................................................................................ 125
Table A. 10. 250ns Timer Base Count [reg08]................................................................................................................... 125
Table A. 11. Tx Impedance Ratio [reg09] .......................................................................................................................... 125
Table A. 12. Tx Post-Cursor Ratio [reg0a] ......................................................................................................................... 125
Table A. 13. Tx Pre-Cursor Ratio [reg0b] .......................................................................................................................... 126
Table A. 14. Power down Feature [reg0e] ........................................................................................................................ 126
Table A. 15. Tx Amplitude Ratio [reg18] ........................................................................................................................... 127
Table A. 16. CDR PLL Frequency Comparator Maximum Difference [reg21] ................................................................... 127
Table A. 17. CDR PLL Frequency Comparator Counter [reg22] ........................................................................................ 127
Table A. 18. EI4 Mode Register [reg23] ............................................................................................................................ 127
Table A. 19. PMA Controller Status [reg30] ...................................................................................................................... 127
Table A. 20. PRBS Control Register [reg64] ...................................................................................................................... 128