Lattice Semiconductor CertusPro-NX Usage Guide

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
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Table A. 21. PRBS Error Counter Register [reg65] ............................................................................................................ 129
Table A. 22. PHY Reset Override Register [reg66] ............................................................................................................ 129
Table A. 23. PHY Power Override Register [reg67] ........................................................................................................... 129
Table A. 24. Transmit PLL Current Charge Pump [reg69] ................................................................................................. 129
Table A. 25. Receive PLL Current Charge Pump [reg6a] ................................................................................................... 130
Table A. 26. PCS Loopback Control [reg74] ...................................................................................................................... 130
Table A. 27. CDR PLL Manual Control [reg79] ................................................................................................................... 131
Table A. 28. PMA Status [reg7f] ........................................................................................................................................ 131
Table A. 29. Update Settings Command Register [reg80] ................................................................................................ 132
Table A. 30. Register Address ........................................................................................................................................... 132
Table A. 31. MPCS Data Path Selection [reg00] ................................................................................................................ 134
Table A. 32. Tx Path Control [reg10] ................................................................................................................................. 135
Table A. 33. 8B/10B Encoder Control [reg11] ................................................................................................................... 135
Table A. 34. Rx Path Control [reg20] ................................................................................................................................. 136
Table A. 35. MPCS Rx Path Status [reg21] ........................................................................................................................ 136
Table A. 36. 8B/10B Decoder Control [reg22] .................................................................................................................. 137
Table A. 37. Word Alignment Control [reg30] .................................................................................................................. 137
Table A. 38. Primary Word Alignment Pattern Byte 0 [reg31].......................................................................................... 137
Table A. 39. Primary Word Alignment Pattern Byte 1 [reg32].......................................................................................... 138
Table A. 40. Primary Word Alignment Pattern MSB [reg33] ............................................................................................ 138
Table A. 41. Secondary Word Alignment Pattern Byte 0 [reg34] ..................................................................................... 138
Table A. 42. Secondary Word Alignment Pattern Byte 1 [reg35] ..................................................................................... 138
Table A. 43. Secondary Word Alignment Pattern MSB [reg36] ........................................................................................ 138
Table A. 44. Word Alignment Pattern Mask Code Byte 0 [reg37] .................................................................................... 138
Table A. 45. Word Alignment Pattern Mask Code Byte 1 [reg38] .................................................................................... 138
Table A. 46. Word Alignment Pattern Mask Code MSB [reg39] ....................................................................................... 139
Table A. 47. Sync_Det FSM Configuration 0 [reg3a] ......................................................................................................... 139
Table A. 48. Sync_Det FSM Configuration 1 [reg3b] ......................................................................................................... 139
Table A. 49. Sync_Det FSM Configuration 2 [reg3c] ......................................................................................................... 139
Table A. 50. Sync_Det FSM Configuration 3 [reg3d] ......................................................................................................... 139
Table A. 51. Number of Bit Slipped during Word Alignment [reg3e] ............................................................................... 140
Table A. 52. Primary Sync_Det Pattern Byte 0 [reg3f] ...................................................................................................... 140
Table A. 53. Primary Sync_Det Pattern Byte 1 [reg40] ..................................................................................................... 140
Table A. 54. Primary Sync_Det Pattern Byte 2 [reg41] ..................................................................................................... 140
Table A. 55. Primary Sync_Det Pattern Byte 3 [reg42] ..................................................................................................... 140
Table A. 56. Primary Sync_Det Pattern Byte MSB [reg43] ................................................................................................ 140
Table A. 57. Secondary Sync_Det Pattern Byte 0 [reg44] ................................................................................................. 141
Table A. 58. Secondary Sync_Det Pattern Byte 1 [reg45] ................................................................................................. 141
Table A. 59. Secondary Sync_Det Pattern Byte 2 [reg46] ................................................................................................. 141
Table A. 60. Secondary Sync_Det Pattern Byte 3 [reg47] ................................................................................................. 141
Table A. 61. Secondary Sync_Det Pattern Byte MSB [reg48] ........................................................................................... 141
Table A. 62. Sync_Det Pattern Mask Code Byte 0 [reg49] ................................................................................................ 141
Table A. 63. Sync_Det Pattern Mask Code Byte 1 [reg4a] ................................................................................................ 141
Table A. 64. Sync_Det Pattern Mask Code Byte 2 [reg4b] ................................................................................................ 141
Table A. 65. Sync_Det Pattern Mask Code Byte 3 [reg4c] ................................................................................................ 141
Table A. 66. Sync_Det Pattern Mask Code MSB [reg4d] ................................................................................................... 141
Table A. 67. Lane Alignment Control [reg50] .................................................................................................................... 142
Table A. 68. Maximum Lane-to-lane Skew [reg51] ........................................................................................................... 142
Table A. 69. Primary Lane Alignment Pattern Byte 0 [reg52] ........................................................................................... 142
Table A. 70. Primary Lane Alignment Pattern Byte 1 [reg53] ........................................................................................... 142
Table A. 71. Primary Lane Alignment Pattern Byte 2 [reg54] ........................................................................................... 142
Table A. 72. Primary Lane Alignment Pattern Byte 3 [reg55] ........................................................................................... 143
Table A. 73. Primary Lane Alignment Pattern Byte MSB [reg56] ...................................................................................... 143
Table A. 74. Secondary Lane Alignment Pattern Byte 0 [reg57] ....................................................................................... 143

Lattice Semiconductor CertusPro-NX Specifications

General

Brand	Lattice Semiconductor
Model	CertusPro-NX
Category	Computer Hardware
Language	English