Lattice Semiconductor CertusPro-NX Usage Guide

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
FPGA-TN-02245-0.81 © 2020-2021 Lattice Semiconductor 9
All rights reserved. CONFIDENTIAL
Table A. 75. Secondary Lane Alignment Pattern Byte 1 [reg58] ....................................................................................... 143
Table A. 76. Secondary Lane Alignment Pattern Byte 2 [reg59] ....................................................................................... 143
Table A. 77. Secondary Lane Alignment Pattern Byte 3 [reg5a] ....................................................................................... 143
Table A. 78. Secondary Lane Alignment Pattern Byte MSB [reg5b] ................................................................................. 143
Table A. 79. Lane Alignment Pattern Mask Code [reg5c] ................................................................................................. 143
Table A. 80. Clock Frequency Compensation Control [reg60] .......................................................................................... 144
Table A. 81. SKIP Pattern Insertion/Deletion Control [reg61] .......................................................................................... 144
Table A. 82. Elastic FIFO High Water Line [reg62] ............................................................................................................ 144
Table A. 83. Elastic FIFO Low Water Line [reg63] ............................................................................................................. 145
Table A. 84. Primary SKIP Pattern Byte 0 [reg64] ............................................................................................................. 145
Table A. 85. Primary SKIP Pattern Byte 1 [reg65] ............................................................................................................. 145
Table A. 86. Primary SKIP Pattern Byte 2 [reg66] ............................................................................................................. 145
Table A. 87. Primary SKIP Pattern Byte 3 [reg67] ............................................................................................................. 145
Table A. 88. Primary SKIP Pattern MSB [reg68] ................................................................................................................ 145
Table A. 89. Secondary SKIP Pattern Byte 0 [reg69] ......................................................................................................... 145
Table A. 90. Secondary SKIP Pattern Byte 1 [reg6a] ......................................................................................................... 145
Table A. 91. Secondary SKIP Pattern Byte 2 [reg6b] ......................................................................................................... 145
Table A. 92. Secondary SKIP Pattern Byte 3 [reg6c] ......................................................................................................... 145
Table A. 93. Secondary SKIP Pattern MSB [reg6d] ............................................................................................................ 146
Table A. 94. SKIP Pattern Mask Code [reg6e] ................................................................................................................... 146
Table A. 95. 64B/66B PCS Tx Path Control [reg80] ........................................................................................................... 146
Table A. 96. 64B/66B PCS Tx FIFO Almost Full Setting Control [reg81] ............................................................................ 146
Table A. 97. 64B/66B PCS Tx FIFO Almost Empty Setting Control [reg82] ....................................................................... 146
Table A. 98. 64B/66B PCS Rx Path Control [reg83] ........................................................................................................... 146
Table A. 99. 64B/66B PCS CTC High Water Line Control [reg84] ...................................................................................... 147
Table A. 100. 64B/66B PCS CTC Low Water Line Control [reg85] ..................................................................................... 147
Table A. 101. 64B/66B PCS Block Align Shift [reg86] ........................................................................................................ 147
Table A. 102. 10GBASE-R BER Counter [reg90] ................................................................................................................ 147
Table A. 103. 10GBASE-R Block Error Counter [reg91] ..................................................................................................... 148
Table A. 104. 10GBASE-R Test Pattern Seed A Byte 0 [reg92] .......................................................................................... 148
Table A. 105. 10GBASE-R Test Pattern Seed A Byte 1 [reg93] .......................................................................................... 148
Table A. 106. 10GBASE-R Test Pattern Seed A Byte 2 [reg94] .......................................................................................... 148
Table A. 107. 10GBASE-R Test Pattern Seed A Byte 3 [reg95] .......................................................................................... 148
Table A. 108. 10GBASE-R Test Pattern Seed A Byte 4 [reg96] .......................................................................................... 148
Table A. 109. 10GBASE-R Test Pattern Seed A Byte 5 [reg97] .......................................................................................... 148
Table A. 110. 10GBASE-R Test Pattern Seed A Byte 6 [reg98] .......................................................................................... 148
Table A. 111. 10GBASE-R Test Pattern Seed A Byte 7 [reg99] .......................................................................................... 149
Table A. 112. 10GBASE-R Test Pattern Seed B Byte 0 [reg9a] .......................................................................................... 149
Table A. 113. 10GBASE-R Test Pattern Seed B Byte 1 [reg9b] .......................................................................................... 149
Table A. 114. 10GBASE-R Test Pattern Seed B Byte 2 [reg9c] .......................................................................................... 149
Table A. 115. 10GBASE-R Test Pattern Seed B Byte 3 [reg9d] .......................................................................................... 149
Table A. 116. 10GBASE-R Test Pattern Seed B Byte 4 [reg9e] .......................................................................................... 149
Table A. 117. 10GBASE-R Test Pattern Seed B Byte 5 [reg9f] ........................................................................................... 149
Table A. 118. 10GBASE-R Test Pattern Seed B Byte 6 [rega0] .......................................................................................... 149
Table A. 119. 10GBASE-R Test Pattern Seed B Byte 7 [rega1] .......................................................................................... 149
Table A. 120. 10GBASE-R Test Pattern Control 0 [rega2] ................................................................................................. 150
Table A. 121. 10GBASE-R Test Pattern Control 1 [rega3] ................................................................................................. 150
Table A. 122. 10GBASE-R Test Pattern Error Counter Byte 0 [rega4] ............................................................................... 151
Table A. 123. 10GBASE-R Test Pattern Error Counter Byte 1 [rega5] ............................................................................... 151
Table A. 124. PMA Control [regc6] ................................................................................................................................... 151
Table A. 125. PMA Control [regc7] ................................................................................................................................... 151
Table A. 126. Loopback Mode Control [rege0] ................................................................................................................. 152
Table A. 127. MPCS BIST Control 0 [rege1] ....................................................................................................................... 152
Table A. 128. MPCS BIST Control 1 [rege2] ....................................................................................................................... 153

Lattice Semiconductor CertusPro-NX Specifications

General

Brand	Lattice Semiconductor
Model	CertusPro-NX
Category	Computer Hardware
Language	English