Newport XPS-D Programmer's Manual

XPS Unified Programmer’s Manual
6.5.3 Status, Error, and High Nibble P2 Interface Register
This register contains the status bits, error bits, and the 4 high order position data bits.
The table below lists the bit positions of these signals in the register. See “Error
Detection and Status Reporting” section for more information. The bits that correspond
to fatal errors are indicated by “(F)”.
Table 3-4 Status, Error, and High Nibble P2 Interface Register Bit Positions
Bit
Description
XPS group state after detection
0
1 (not used)
1
1 (not used)
2
1 (not used)
3
1 (not used)
4
1 (not used)
5
1 (not used)
6
1 (not used)
7
1 (not used)
8
1 (not used)
9
1 (not used)
10
1 (not used)
11
User Bit
12
Position Data bit 32
13
Position Data bit 33
14
Position Data bit 34
15
Position Data bit 35
16
Reference Signal Present
17
Reference PLL Locked
18
System OK
19
Measurement Signal Present
20
Position Reset Complete
21
(F) Reference Signal Missing
Not init
22
(F) Reference PLL Error
Not init
23
(F) System Error
Not init
24
(F) Measure Signal Missing
Not init
25
(F) Measure Signal Dropout
Not init
26
(F) Measure Signal Glitch
Not init
27
(F) Velocity Error
28
User Velocity Error
29
(F) Acceleration Error
30
(F) 36 bit Position Overflow
Not init
31
32 bit Position Overflow
Not init
The high nibble bits are latched at the same time as the P2 Position register, and should
be read after the position is read. The error bits (21-31) have the same meaning as the
corresponding errors in the VME Error Status register (bits 0-10). The P2 Error register
is set and reset separately from the VME Error Status register.
The status bits (16-20) have the same meaning as the corresponding status bits in the
VME Status Register (bits 0-4). The User Bit shows the state of the User P2 bit in VME
Control Register 1.
EDH0373En1023 — 01/18 38

Newport XPS-D Specifications

General

Brand	Newport
Model	XPS-D
Category	Controller
Language	English