Newport XPS-D Programmer's Manual

XPS Unified Programmer’s Manual
6.5.5 PEG Control Register
The bit assignments of the PEG Control register are listed below. The PEG Enable
Control and PEG Disable Control fields control the overall operation of the PEG
subsystem.
Bit Description
1:0
PEG Pulse Width (00 = 25 ns, 01 = 50 ns, 10 = 75 ns, 11 = 100 ns)
2
Enable P1->P2 operation
3
Enable P2->P1 operation
4
PEG Axis Select (0 = axis 1, 1 = axis 2)
5
PEG Output Enable
6
PEG Output Polarity (0 = Low pulse, 1 = High pulse)
7
Enable Delta 2
10:8
PEG Disable Control
0 = NO_EXIT = Don’t disable
1 = P1_EXIT = Disable at P1 exit
2 = P2_EXIT = Disable at P2 exit
3 = ANY_EXIT = Disable at P1 or P2 exit
4 = IMM_EXIT = Disable immediately
11
PEG P2 Delta (0 = Delta 1, 1 = Delta 2)
13:12
PEG Enable Control
0 = NO_ENT = Don’t enable
1 = P1_ENT = Enable at P1 entry
2 = P2_ENT = Enable at P2 entry
3 = ANY_ENT = Enable at P1 or P2 entry
15:14
Reserved
6.5.6 ZYGO Axis Error Status List
code
Error Status description
Error mask
0
Success
0x0001
Reference signal is missing
1
0x0002
Reference PLL Error
1
0x0004
System Error
1
0x0008
Measure Signal Missing
1
0x0010
Measure Signal Dropout
0
0x0020
Measure Signal Glitch
1
0x0040
Velocity Error
1
0x0100
Acceleration Error
0
0x0200
36 bit Position Overflow
1
0x0400
32 bit Position Overflow
1
0x0800
P2 External Sample
0
0x1000
Not used
0
0x2000
PEG Error
0
0x4000
Not used
0
0x8000
IRQ Pending
0
The axis error status register is read via Ethernet. A XPS controller error is generates
when one or several bits of Error mask are ON. In this case, the group goes to
NOTINIT state.
EDH0373En1023 — 01/18 40

Newport XPS-D Specifications

General

Brand	Newport
Model	XPS-D
Category	Controller
Language	English