Sel SEL-787 - Page 14

xii List of Figures
SEL-787 Relay Instruction Manual Date Code 20150130
Figure 4.6 Differential Current Alarm Logic Diagram............................................................................. 4.11
Figure 4.7 Winding Connections, Phase Shifts, and Compensation Direction......................................... 4.17
Figure 4.8 Example 1 for WnCTC Selection............................................................................................ 4.19
Figure 4.9 Example 2 for WnCTC Selection............................................................................................ 4.21
Figure 4.10 SEL-787 Differential Characteristics (Preferred and Other)................................................... 4.23
Figure 4.11 REF Directional Element......................................................................................................... 4.30
Figure 4.12 REF1 Enable Logic.................................................................................................................. 4.31
Figure 4.13 REF1 Directional Element ......................................................................................................4.31
Figure 4.14 REF Element Trip Output........................................................................................................ 4.32
Figure 4.15 Internal Fault With LV Breaker Open......................................................................................4.32
Figure 4.16 REF Protection Output (Extremely Inverse-Time O/C) .......................................................... 4.33
Figure 4.17 Single-Wye Winding REF Application (REF1POL := 2)........................................................4.34
Figure 4.18 Autotransformer REF Application (REF1POL := 12)............................................................. 4.34
Figure 4.19 Instantaneous Overcurrent Element Logic...............................................................................4.36
Figure 4.20 Maximum Phase Time-Overcurrent Elements 51P1T and 51P2T........................................... 4.38
Figure 4.21 Phase A, B, and C Time-Overcurrent Elements ...................................................................... 4.39
Figure 4.22 Residual Time-Overcurrent Elements 51G1T and 51G2T ...................................................... 4.40
Figure 4.23 Negative-Sequence Time-Overcurrent Element 51Q1T and 51Q2T....................................... 4.41
Figure 4.24 Neutral Time-Overcurrent Elements 51N1T and 51N2T........................................................4.42
Figure 4.25 U.S. Moderately Inverse Curve: U1......................................................................................... 4.44
Figure 4.26 U.S. Inverse Curve: U2............................................................................................................4.44
Figure 4.27 U.S. Very Inverse Curve: U3 ................................................................................................... 4.44
Figure 4.28 U.S. Extremely Inverse Curve: U4 .......................................................................................... 4.44
Figure 4.29 U.S. Short-Time Inverse Curve: U5......................................................................................... 4.45
Figure 4.30 IEC Class A Curve (Standard Inverse): C1 .............................................................................4.45
Figure 4.31 IEC Class B Curve (Very Inverse): C2 .................................................................................... 4.45
Figure 4.32 IEC Class C Curve (Extremely Inverse): C3.............................................................................. 4.45
Figure 4.33 IEC Long-Time Inverse Curve: C4.......................................................................................... 4.46
Figure 4.34 IEC Short-Time Inverse Curve: C5.......................................................................................... 4.46
Figure 4.35 Undervoltage Element Logic...................................................................................................4.49
Figure 4.36 Overvoltage Element Logic..................................................................................................... 4.50
Figure 4.37 V/Hz Element Logic................................................................................................................ 4.51
Figure 4.38 Dual-Level Volts/Hertz Time-Delay Characteristic, 24CCS = DD......................................... 4.52
Figure 4.39 Composite Inverse/Definite-Time Overexcitation Characteristic, 24CCS = ID...................... 4.52
Figure 4.40 Volts/Hertz Inverse-Time Characteristic, 24IC = 0.5 ..............................................................4.55
Figure 4.41 Volts/Hertz Inverse-Time Characteristic, 24IC = 1 ................................................................. 4.56
Figure 4.42 Volts/Hertz Inverse-Time Characteristic, 24IC = 2 ................................................................. 4.57
Figure 4.43 Three-Phase Power Elements Logic........................................................................................ 4.58
Figure 4.44 Power Elements Operation in the Real/Reactive Power Plane................................................ 4.59
Figure 4.45 Over- and Underfrequency Element Logic.............................................................................. 4.60
Figure 4.46 Loss-of-Potential (LOP) Logic................................................................................................ 4.62
Figure 4.47 Demand Current Logic Outputs............................................................................................... 4.63
Figure 4.48 Response of Thermal and Rolling Demand Meters to a Step Input
(Setting DMTC = 15 minutes)............................................................................................ 4.64
Figure 4.49 Voltage V
S
Applied to Series RC Circuit ................................................................................ 4.65
Figure 4.50 Trip Logic................................................................................................................................ 4.68
Figure 4.51 Close Logic..............................................................................................................................4.69
Figure 4.52 Schematic Diagram of a Traditional Latching Device............................................................. 4.71
Figure 4.53 Logic Diagram of a Latch Switch............................................................................................ 4.71
Figure 4.54 SEL
OGIC Control Equation Variable/Timers SV01/SV01T–SV32T....................................... 4.73
Figure 4.55 Result of Falling-Edge Operator on a Deasserting Input......................................................... 4.76
Figure 4.56 Example Use of SEL
OGIC Variables/Timers............................................................................4.77
Figure 4.57 Counter 01................................................................................................................................ 4.78