Alcatel-Lucent 7342 - Alexandria FPGA; Complex Programmable Logic Device; Network Synchronization; Time Calibration

6 — LP MDU, MDU, and modular ONT hardware functional blocks
Alcatel-Lucent 7342 ISAM FTTU ONT R04.05.06 July 2008 6-7
3FE 51892 AAAA TCZZA Edition 01 ONT Product Information Manual
Complex programmable logic device
The LP MDU ONT uses the CPLD to decode the address of the control bus interface
and for chip select generation. The CPLD can also be used to provide network timing
referencing (NTR) for Ethernet UNI interfaces.
Network synchronization
The LP MDU ONT subsystems, such as the voice and VDSL2 subsystems, require
voice network synchronization clocks. The NTR is normally derived from the
recovered GPON clock. During a LOS state on the GPON interface, a minimum
32 ppm clock is maintained.
The Alexandria FPGA is responsible for generating the VoIP subsystem and VDSL2
subsystem NTR clock. All other voice network synchronization clocks are locally
generated on the service board.
Time calibration
The LP MDU ONT derives accurate time calibration from a series of NTP servers.
The ONT communicates with the NTP servers using the NTP protocol and
authenticates NTP servers with a provisionable security key.
If NTP is not used, the ONT receives time calibration from the OLT.
Alexandria FPGA
For the GE LP MDU ONT, one of the three blocks found in the service board rather
than the motherboard as with the VDSL2 variant, is the Alexandria FPGA. In the GE
LP MDU ONT, communication between the motherboard and service board,
including the sending of configuration signals, is sent from the motherboard through
the SU connector to the FPGAs in the service board. These FPGAs support POTS
and 10/100/1000BASE-T Ethernet connections.
The VDSL2 LP MDU ONT supports three Alexandria FPGAs. The FPGA is a six
port Ethernet switch that controls functions such as buses, bridges, and interfaces to
the VDSL2 and VoIP DSPs on the service board, and the LEDs on the LP MDU
ONT. Each FPGA supports up to 8 POTS and 4 VDSL2 connections.
For upstream traffic, the FPGA either adds, translates, or replaces VLAN tags based
on the QoS tagging mode specification. For downstream traffic, the FPGA either
strips, translates, or allows to pass through VLAN tags travelling toward UNI ports.
The FPGA supports eight CoS queues for the source synchronous serial MII
(SS-SMII) interfaces respectively associated with a UNI port.
The FPGA performs switching between the VoIP MII interface, the UNI interface,
and the GE port. The FPGA supports egress shaping in the downstream direction
toward the VDSL2 subsystem.
The FPGA is configurable through a serial configuration interface from the PON
motherboard and a JTAG boundary scan interface, which is used for production.
VDSL2 subsystem
The service board provides the VDSL2 subsystem functions as described in
Table 6-8.