Alcatel-Lucent 9500 MXC - Page 429

9500 MXC User Manual
3DB 23063 ADAA - Rev 004 July 2007 Vol. IV-7-39
Figure 7-10. Typical DAC 155oM Line Interface Screen
Item Description
1 Module graphic shows an E1 backplane bus selection (STM1/OC3 trib
multiplexed to/from a 63xE1 backplane bus). Go to Bus Ports to select between
63xE1 or 84xDS1 bus (multiplexer) operation.
2 Select required frame type. SDH operation supports VC3 or VC4 framing
options. SONET operation uses STS1 framing.
3 Select clock mode:
• Recovered takes the clock from the incoming STM1/OC3 signal (loop
timing). Used for most applications.
• Internal selects an internally generated clock source.
4 NMS transport. Select between None, RSOH or MSOH. When a DAC 155oM
link is installed in a 9500 MXC SDH ring, MSOH would normally be used.
5 Signal degrade threshold. Select between the BER default of 10
-6
, and options
for 10
-7
or 10
-8
. When the threshold is exceeded an alarm is raised in the Events
Browser and Alarms screens.
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