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ARTERY AT32F421C8T7 - Page 233

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AT32F421 Series Reference Manual
2022.11.11 Page 233 Rev 2.02
Input capture mode:
Bit
Register
Reset value
Type
Description
Bit 15: 12
C2DF
0x0
rw
Channel 2 digital filter
Bit 11: 10
C2IDIV
0x0
rw
Channel 2 input divider
Bit 9: 8
C2C
0x0
rw
Channel 2 configuration
This field is used to define the direction of the channel 2
(input or output), and the selection of input pin when
C2EN=โ€™0โ€™:
00: Output
01: Input, C2IN is mapped on C2IFP2
10: Input, C2IN is mapped on C1IFP2
11: Input, C2IN is mapped on STCI. This mode works
only when the internal trigger input is selected by STIS.
Bit 7: 4
C1DF
0x0
rw
Channel 1 digital filter
This field defines the digital filter of the channel 1. N
stands for the number of filtering, indicating that the input
edge can pass the filter only after N sampling events.
0000: No filter, sampling is done at f
๐ท๐‘‡๐‘†
1000: f
๐‘†๐ด๐‘€๐‘ƒ๐ฟ๐ผ๐‘๐บ
=f
๐ท๐‘‡๐‘†
/8, N=6
0001: f
๐‘†๐ด๐‘€๐‘ƒ๐ฟ๐ผ๐‘๐บ
=f
๐ถ๐พ_๐ผ๐‘๐‘‡
, N=2
1001: f
๐‘†๐ด๐‘€๐‘ƒ๐ฟ๐ผ๐‘๐บ
=f
๐ท๐‘‡๐‘†
/8, N=8
0010: f
๐‘†๐ด๐‘€๐‘ƒ๐ฟ๐ผ๐‘๐บ
=f
๐ถ๐พ_๐ผ๐‘๐‘‡
, N=4
1010: f
๐‘†๐ด๐‘€๐‘ƒ๐ฟ๐ผ๐‘๐บ
=f
๐ท๐‘‡๐‘†
/16, N=5
0011: f
๐‘†๐ด๐‘€๐‘ƒ๐ฟ๐ผ๐‘๐บ
=f
๐ถ๐พ_๐ผ๐‘๐‘‡
, N=8
1011: f
๐‘†๐ด๐‘€๐‘ƒ๐ฟ๐ผ๐‘๐บ
=f
๐ท๐‘‡๐‘†
/16, N=6
0100: f
๐‘†๐ด๐‘€๐‘ƒ๐ฟ๐ผ๐‘๐บ
=f
๐ท๐‘‡๐‘†
/2, N=6
1100: f
๐‘†๐ด๐‘€๐‘ƒ๐ฟ๐ผ๐‘๐บ
=f
๐ท๐‘‡๐‘†
/16, N=8
0101: f
๐‘†๐ด๐‘€๐‘ƒ๐ฟ๐ผ๐‘๐บ
=f
๐ท๐‘‡๐‘†
/2, N=8
1101: f
๐‘†๐ด๐‘€๐‘ƒ๐ฟ๐ผ๐‘๐บ
=f
๐ท๐‘‡๐‘†
/32, N=5
0110: f
๐‘†๐‘€๐‘ƒ๐ฟ๐ผ๐‘๐บ
=f
๐ท๐‘‡๐‘†
/4, N=6
1110: f
๐‘†๐ด๐‘€๐‘ƒ๐ฟ๐ผ๐‘๐บ
=f
๐ท๐‘‡๐‘†
/32, N=6
0111: f
๐‘†๐ด๐‘€๐‘ƒ๐ฟ๐ผ๐‘๐บ
=f
๐ท๐‘‡๐‘†
/4, N=8
1111: f
๐‘†๐ด๐‘€๐‘ƒ๐ฟ๐ผ๐‘๐บ
=f
๐ท๐‘‡๐‘†
/32, N=8
Bit 3: 2
C1IDIV
0x0
rw
Channel 1 input divider
This field defines Channel 1 input divider.
00: No divider. An input capture is generated at each
active edge.
01: An input compare is generated every 2 active edges
10: An input compare is generated every 4 active edges
11: An input compare is generated every 8 active edges
Note: the divider is reset once C1EN=โ€™0โ€™
Bit 1: 0
C1C
0x0
rw
Channel 1 configuration
This field is used to define the direction of the channel 1
(input or output), and the selection of input pin when
C1EN=โ€™0โ€™:
00: Output
01: Input, C1IN is mapped on C1IFP1
10: Input, C1IN is mapped on C2IFP1
11: Input, C1IN is mapped on STCI. This mode works
only when the internal trigger input is selected by STIS.

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