ARTERY AT32F421C8T7 - Page 5

AT32F421 Series Reference Manual
2022.11.11 Page 5 Rev 2.02
6 General-purpose I/Os (GPIOs) ....................................................... 82
6.1 Introduction ................................................................................. 82
6.2 Functional overview ..................................................................... 82
6.2.1 GPIO structure ............................................................................ 82
6.2.2 GPIO reset status ........................................................................ 82
6.2.3 General-purpose input configuration ............................................. 83
6.2.4 Analog input/output configuration ................................................. 83
6.2.5 General-purpose output configuration ........................................... 83
6.2.6 GPIO port protection ................................................................... 83
6.2.7 IOMUX structure ......................................................................... 84
6.2.8 Multiplexed function input configuration ........................................ 84
6.2.9 IOMUX function input/output ........................................................ 85
6.2.10 Peripheral multiplexed function configuration ................................ 87
6.2.11 IOMUX map priority ..................................................................... 87
6.2.12 External interrupt/wake-up lines ................................................... 87
6.3 GPIO registers ............................................................................. 87
6.3.1 GPIO configuration register (GPIOx_CFGR) (x=A…H) ................... 88
6.3.2 GPIO input mode register (GPIOx_OMODE) (x=A…H) ................... 88
6.3.3 GPIO drive capability register (GPIOx_ODRVR) (x=A..H) ............... 88
6.3.4 GPIO pull-up/pull-down register (GPIOx_PULL) (x=A..H) ............... 88
6.3.5 GPIO input data register (GPIOx_IDT) (x=A…H) ........................... 89
6.3.6 GPIO output data register (GPIOx_ODT) (x= A…H) ....................... 89
6.3.7 GPIO set/clear register (GPIOx_SCR) (x=A…H) ............................ 89
6.3.8 GPIO write protection register (GPIOx_WPR) (x=A…H) ................. 89
6.3.9 GPIO multiplexed function low register (GPIOx_MUXL) (x=A..H) .... 90
6.3.10 GPIO multiplexed function high register (GPIOx_MUXH) (x=A..H) .. 90
6.3.11 GPIO bit clear register (GPIOx_CLR) (x=A…H) ............................. 90
6.3.12 GPIO huge current control register (GPIOx_HDRV) (x=A..H) .......... 90
7 System configuration controller (SCFG) ....................................... 91
7.1 Introduction ................................................................................. 91
7.2 SCFG registers ............................................................................ 91
7.2.1 SCFG configuration register1 (SCFG_CFG1) ................................ 91
7.2.2 SCFG external interrupt configuration register1 (SCFG_ EXINTC1) 92
7.2.3 SCFG external interrupt configuration register2 (SCFG_ EXINTC2) 93