ARTERY AT32F421C8T7 - Page 6

AT32F421 Series Reference Manual
2022.11.11 Page 6 Rev 2.02
7.2.4 SCFG external interrupt configuration register3 (SCFG_ EXINTC3) 93
7.2.5 SCFG external interrupt configuration register4 (SCFG_ EXINTC4) 94
8 External interrupt/Event controller (EXINT) .................................. 95
8.1 EXINT introduction ....................................................................... 95
8.2 Function overview and configuration procedure .............................. 95
8.3 EXINT registers ........................................................................... 96
8.3.1 Interrupt enable register (EXINT_INTEN) ...................................... 96
8.3.2 Event enable register (EXINT_EVTEN) ......................................... 96
8.3.3 Polarity configuration register1 (EXINT_ POLCFG1) ...................... 96
8.3.4 Polarity configuration register2 (EXINT_ POLCFG2) ...................... 97
8.3.5 Software trigger register (EXINT_ SWTRG) ................................... 97
8.3.6 Interrupt status register (EXINT_ INTSTS) .................................... 97
9 DMA controller (DMA) ................................................................... 98
9.1 Introduction ................................................................................. 98
9.2 Main features .............................................................................. 98
9.3 Functional overview ..................................................................... 98
9.3.1 DMA configuration ....................................................................... 98
9.3.2 Handshake mechanism ................................................................ 99
9.3.3 Arbiter ........................................................................................ 99
9.3.4 Programmable data transfer width ............................................... 100
9.3.5 Errors ........................................................................................ 101
9.3.6 Interrupts ................................................................................... 101
9.3.7 Fixed DMA request mapping ....................................................... 101
9.4 DMA registers ............................................................................ 102
9.4.1 DMA interrupt status register (DMA_STS) .................................... 103
9.4.2 DMA interrupt flag clear register (DMA_CLR) ............................... 104
9.4.3 DMA channel-x configuration register (DMA_CxCTRL) (x = 1…5)105
9.4.4 DMA channel-x number of data register (DMA_CxDTCNT) (x = 1…5)106
9.4.5 DMA channel-x peripheral address register (DMA_CxPADDR) (x = 1…5)
106
9.4.6 DMA channel-x memory address register (DMA_CxMADDR) (x = 1…5)106
10 CRC calculation unit (CRC) ......................................................... 107