ARTERY AT32F421C8T7 - Page 7

AT32F421 Series Reference Manual
2022.11.11 Page 7 Rev 2.02
10.1 CRC introduction ....................................................................... 107
10.2 CRC registers ............................................................................ 107
10.2.1 Data register (CRC_DT).............................................................. 107
10.2.2 Common data register (CRC_CDT) .............................................. 107
10.2.3 Control register (CRC_CTRL) ...................................................... 108
10.2.4 Initialization register (CRC_IDT) ................................................. 108
11 I
2
C interface ................................................................................ 109
11.1 I
2
C introduction .......................................................................... 109
11.2 I
2
C main features ....................................................................... 109
11.3 I
2
C functional overview ............................................................... 109
11.4 I
2
C interface .............................................................................. 110
11.4.1 I
2
C slave communication flow ...................................................... 111
11.4.2 I
2
C master communication flow ................................................... 114
11.4.3 Data transfer using DMA ............................................................. 120
11.4.4 SMBus ....................................................................................... 121
11.4.5 I
2
C interrupt requests ................................................................. 122
11.4.6 I
2
C debug mode ......................................................................... 123
11.5 I
2
C registers .............................................................................. 123
11.5.1 Control register1 (I2C_CTRL1) .................................................... 123
11.5.2 Control register2 (I2C_CTRL2) .................................................... 124
11.5.3 Own address register1 (I2C_OADDR1) ........................................ 125
11.5.4 Own address register2 (I2C_OADDR2) ........................................ 125
11.5.5 Data register (I2C_DT) ............................................................... 126
11.5.6 Status register1 (I2C_STS1) ....................................................... 126
11.5.7 Status register2 (I2C_STS2) ....................................................... 128
11.5.8 Clock control register (I2C_ CLKCTRL) ....................................... 129
11.5.9 Clock rise time register (I2C_TMRISE) ........................................ 129
12 Universal synchronous/asynchronous receiver/transmitter (USART)130
12.1 USART introduction ................................................................... 130
12.2 Full-duplex/half-duplex selector .................................................. 132
12.3 Mode selector ............................................................................ 132
12.3.1 Introduction................................................................................ 132
12.3.2 Configuration procedure ............................................................. 132