ARTERY AT32F421C8T7 - Page 8

AT32F421 Series Reference Manual
2022.11.11 Page 8 Rev 2.02
12.4 USART frame format and configuration ........................................ 136
12.5 DMA transfer introduction ........................................................... 137
12.5.1 Transmission using DMA ............................................................ 137
12.5.2 Reception using DMA ................................................................. 137
12.6 Baud rate generation .................................................................. 138
12.6.1 Introduction................................................................................ 138
12.6.2 Configuration ............................................................................. 138
12.7 Transmitter ................................................................................ 139
12.7.1 Transmitter introduction .............................................................. 139
12.7.2 Transmitter configuration ............................................................ 139
12.8 Receiver ................................................................................... 140
12.8.1 Receiver introduction .................................................................. 140
12.8.2 Receiver configuration ................................................................ 140
12.8.3 Start bit and noise detection ....................................................... 141
12.9 Tx/Rx swap ............................................................................... 142
12.10Interrupt requests ...................................................................... 142
12.11I/O pin control............................................................................ 143
12.12USART registers ........................................................................ 143
12.12.1 Status register (USART_STS) .................................................. 144
12.12.2 Data register (USART_DT) ....................................................... 145
12.12.3 Baud rate register (USART_BAUDR) ........................................ 145
12.12.4 Control register1 (USART_CTRL1) ........................................... 145
12.12.5 Control register2 (USART_CTRL2) ........................................... 146
12.12.6 Control register3 (USART_CTRL3) ........................................... 147
12.12.7 Guard time and divider register (USART_GDIV) ........................ 148
13 Serial peripheral interface (SPI) .................................................. 149
13.1 SPI introduction ......................................................................... 149
13.2 Functional overview ................................................................... 149
13.2.1 SPI description ........................................................................... 149
13.2.2 Full-duplex/half-duplex selector .................................................. 150
13.2.3 Chip select controller .................................................................. 152
13.2.4 SPI_SCK controller .................................................................... 152
13.2.5 CRC .......................................................................................... 152